The second installment of a series on reverse engineering the Transmeta TM5xxx Architecture
Though my background is primarily on the software side, I am very curious about the effects that different processor designs and features have on system performance. Being somewhat less knowledgeable about CPU architecture than many others, I have been looking for some way to see these effects in a concrete manner. Benchmarks are supposed to provide this ‘visible’ evidence, but there are probably as many different application mixes and workloads as there are users. This isn’t a problem for a corporation that has the money to spend to evaluate how their applications and workloads will perform on a given platform – but the average user, such as myself, is left wondering what these benchmarks are really measuring so they can be applied to our own usage.
A detailed examination of two high end server microprocessors, the Alpha EV8 and the IA64 McKinley, based on recent and extensive disclosures at ISSCC 2002.
Paul DeMone takes a look at what significant events may occur in the MPU market in the coming year.
An examination of the design weaknesses in the Intel Itanium
processor and speculation on the many possible ways that the 2nd
generation McKinley processor could have improved on Itanium.
Recently released benchmarks for the new Pentium 4 processor look disappointing – but is it really a slug or a sleeper? Paul DeMone takes a close look at the SPEC numbers to divine the processor’s potential.
IBM unveils a powerful 64-bit processor that may put them in the front of the performance race. Paul dissects it in this months Silicon Insider.
Paul investigates why Willamette has only an 8 KB L1 cache, and why he feels this is beneficial to performance.
This is the second of a two-part series in which Paul DeMone dissects the upcoming Willamette processor from Intel. In this installment Paul looks at the trace cache and ALU in detail, and speculates on what the performance might be.