22nm Design Challenges at ISSCC 2011

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Design Challenges at 22nm

This year at ISSCC, our friend Don Draper (of True Circuits) moderated a panel discussion on the design and manufacturing challenges and trends for 22nm CMOS logic. One of the panel goals was to expose the design community to the perspectives of leading edge semiconductor manufacturers. Given the increasing trend towards a separation of design and manufacturing (into fabless companies and foundries), bridging the gap becomes ever more important. The speakers included a number of high profile process technology experts. Mark Bohr of Intel represented the only pure play integrated device manufacturer (IDM) perspective; Bill Liu from Global Foundries and Min Cao of TSMC spoke from the standpoint of the foundries. Ghavam Shahidi of IBM was somewhat of a blend of the two, albeit with emphasis on the IDM side. Koichiro Ishibashi of Renesas and the audience largely represented the designer perspective.

There was a general consensus between the different speakers that, looking forward, the chief challenges for semiconductor manufacturing and design are primarily variability related. The hard truth is that when placing billions of transistors and kilometers of interconnect, statistics dictates that the results are not deterministic, but probabilistic. Many physical phenomena that were once minor edge effects are now increasingly important. For example, the same 1nm variation in gate length is relatively larger for minimum size gates in a 22nm process than a 45nm one. The change in gate length is often called line edge roughness (LER) and is largely a result of using 193nm light to draw features which are nearly an order of magnitude smaller.

The single biggest cause of variation is random dopant fluctuation (RDF), where the dopant atoms that are implanted in the transistor channel are unevenly distributed. Once this was not an issue, however the size of transistors and the number of dopant atoms small enough that the density can fluctuate significantly.

Other contributors to variation are systematic, rather than random, and determined by the context of a transistor. Transistors can impact the performance of their neighbors, so a single transistor cannot be considered in isolation and depends on the context. For instance, strained silicon improves transistor performance, the strain is impacted by nearby layout structures.

These physical effects (and many others) cause substantial variation in the threshold voltage (Vt) of transistors if left unchecked. At the chip level, this can have a huge impact on idle and active power consumption and performance, since engineers must always accommodate the worst case scenario. Leakage is an exponential function of both temperature and threshold voltage, so even a modest change in Vt can substantially alter power consumption – especially across a few billion transistors. For key structures like SRAM, it is important that matched transistors have nearly identical Vt. Variation between matched transistors increases the likelihood of a read error and designers must increase the SRAM supply voltage to compensate, which quadratically increases active power consumption. Even worse, most chips are designed with a 5-7 year life time and variability certainly does not improve with age. As variability drives up both idle and active power consumption, this limits the operating frequency and reduces overall performance.

While this may sound theoretical and abstract, it is critically important and visible even to consumers. A paper from Qualcomm at IEDM 2010 showed that when variation worsened by ~2.5X, the full chip leakage power shot up by ~3X, in a 28nm low power process. Nvidia’s experience with their first generation of 40nm GPUs highlights the challenges and was one of the first times that manufacturing became a publicly contentious issue. The first Fermi products were delayed by 3-6 months and the early versions suffered from power problems that strongly suggest variation as the chief culprit.

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