22nm Design Challenges at ISSCC 2011

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Consensus at 22nm

The consensus from the panelists is that 22nm will be an evolutionary step from 32nm. Like the processes described at IEDM 2008 and IEDM 2010, bulk silicon will be the norm, using 193nm immersion lithography with multiple exposures. TSMC noted that high-k/metal gates have a huge advantage, reducing Vt variation by roughly 30% and will practically be a requirement at this node, with gate-last as the implementation choice.

The adoption of high-k/metal gates substantially reduced leakage at the 45nm (Intel) and 32nm (TSMC, GF, IBM) nodes. Since no major advances along these lines are expected, leakage will get worse at the 22nm node and become even more of a challenge for designers. This in turn will place greater emphasis on techniques which reduce leakage such as multiple Vt devices and power gating.

Another key area of consensus is that co-optimization between manufacturing and circuit design is necessary for success, especially for anyone interested in cutting edge work. Rather than having a discrete hand-off between manufacturing and design, a co-operative and iterative approach where trade-offs are considered jointly is needed. Intel was a pioneer with early use of restrictive design rules (RDRs) on the 65nm node to facilitate higher performance and yields. Co-optimization is easier for IDMs, but is increasingly necessary to achieve the benefits of a new node.

One example of co-optimzation cited by panelists is the increased focus of manufacturers on improving PMOS performance. As PMOS and NMOS performance become closer, the benefits of dynamic logic (which favors NMOS over PMOS) are substantially reduced – eliminating a considerable source of complexity for circuit designers.

However, most of the trade-offs tend to run in the other direction, with RDRs sacrificing some design freedom for substantially better results in silicon. Some examples include restricting transistor orientation to run in a single direction (i.e. 1D vs. 2D), with no jogs or bends. The transistor placement can be constrained to align with a grid that is somewhat coarser grain than the lithography allows (e.g. transistors must be aligned to a 30nm grid). The possible transistor gate lengths can also be restricted to a small number of options, rather than allowing arbitrary gate lengths. Similarly, the design rules might require a larger area overlap on the connection between metal interconnect layers and the vertical vias, to prevent potential failures.

The trade-offs involved with RDRs are very real. TSMC has reported that gate density improves by 1.6X with RDRs, versus 2X for unconstrained designs, although with proper design effort, this penalty is reduced. The advantage is that the enforced regularity substantially reduces variation and has a huge benefit for performance, power and yield. While the foundries have tried to delay adopting RDRs as long as possible, they are a clear necessity at 22nm and beyond. The key to success is collaboration between design and manufacturing to select the restrictions with the right cost/benefit balance.

TSMC also pointed out that RDRs are most useful for performance sensitive regions of a chip. Separate design rules can be used for low performance. For instance, large always-on components in an SOC that operate at low frequency do not benefit much from RDRs and would favor from design rules that favor density instead of performance and leakage reduction. A hybrid strategy that uses restrictive and density design rules in different macro-blocks in a chip should be the most effective going forward.

Everyone emphasized the yield, performance and power benefits of a forward thinking and flexible design philosophy for cutting edge development. Both Global Foundries and TSMC focused on early test shuttles with high logic content (rather than just SRAM) to avoid late stage surprises. The two foundries were equally cognizant that process characterization and design rule changes are an unpleasant but inevitable aspect of working with a cutting edge process technology. Designers must leave themselves enough room to adapt to any such surprises, since they rarely tend to be favorable.

Another common theme was circuit techniques that improve scaling. Ishibashi-san highlighted Renesas’ work on body biasing, which mitigates variation by tuning Vt after fabrication. Dr. Cao highlighted the benefits of read and write assist circuits for SRAMs, which reduce the minimum operating voltage and thus power consumption.

Another sign of consensus was Mark Bohr’s claim that the era of ‘one size fits all’ manufacturing is at an end and that foundries and IDMs must accommodate the increasing variety of modern chip designs. While this is hardly news for any of the foundries, it certainly marks a departure for Intel, as they begin to focus more and more on the SOC and low power market. It also has implications for IBM, which has an even greater focus on high performance at the expense of cost and power consumption.

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