Editor’s Note: This article is the first from Euronymous, an anonymous contributor to Real World Tech. This report is focused on 3D integration and largely based on material from the 39th Annual International Symposium on Microarchitecture, known as MICRO-39. MICRO is one of the premier forums for new research on microarchitecture. Unlike MPF or ISSCC, the discussion mainly focuses on research for future directions, rather than existing or imminent products. Each MICRO is composed of several tutorials and workshops, each focusing on a distinct area. Of the tutorials at MICRO-39, one of the most popular was “3D Integration for (Micro)Architects”, which featured speakers from IBM, Intel, UCLA, Penn State and Georgia Tech discussing 3D integration, a novel method of building multi-layer semiconductor devices.
The continuing pace of chip level feature miniaturization – Moore’s Law – has resulted in the doubling of the number of transistors per unit area approximately every couple of years. Chip designers have been provided with a plethora of transistor options to choose from in order to optimize for a given constraint. New materials with higher dielectric constants such as hafnium-based high-k gate oxide materials , along with metal gate electrodes, decrease leakage and boost drive current. Strained silicon engineering  enables higher transistor switching speeds. Different transistor designs featuring multiple threshold voltages optimize for low power or high performance applications. New transistor structures such as the double or the tri-gate  transistor enable further increases in device switching speeds while reducing leakage. Fundamentally, these improvements have concentrated on transistors, while interconnect performance has languished and fallen behind these new and faster transistors.
Three dimensional integration uses multiple vertical layers of transistors to improve performance, instead of the single layer of transistors that most modern integrated circuits use today. This report presents the interconnect problem, which is a major motivator for three dimensional integrated circuits and explains in detail how three dimensional integration will improve performance for modern integrated circuits and preliminary results for a 3D microprocessor.