3D Integration: A Revolution in Design

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3D Bonding and Yield

The final 3D IC fabrication issue facing semiconductor engineers is manufacturing yield and testing. The 3D stack can be assembled at the wafer scale, before testing, or at the tested die level. The wafer to wafer bonding technique assembles whole wafers to each other resulting in high manufacturing throughput [11]. Afterwards, the processed wafers are sliced and tested. Overall, wafer to wafer bonding should have a positive effect on yield if designers use 3D integration to reduce the size of each individual die.

Wafer to wafer bonding of large dice has a detrimental effect on yield, since as more wafers are stacked together, the more likely the whole chip stack is to be ruined by one bad layer. Assuming that the stacked dice are about the same size, with a die yield of 80%, a two die stack will yield at 64%, not counting stacks lost due to attachment. So designers are not likely to view as 3D integration as a tool to substantially increase die size for integrated circuits.

However, the resulting stacked dice do not need to be of equal size. If the designers stack two dice that are about half the size of the original integrated circuit, yields will actually improve. Specifically, breaking a planar die into multiple smaller pieces will increase the yield of the smaller dice, since more candidate dice can fit in a given wafer. Because there are more candidate dice per wafer, the number of defects (which should be roughly constant), will effect a smaller percentage of the overall number of candidate dice. Figure 9 below illustrates the benefits of wafer to wafer bonding on yield for a simple two layer stack. Note that the benefits of additional stacks decreases (even with perfectly sub-divisible integrated circuits) and eventually will reduce yield because the attachment process is not perfect. For example, a 100 layer stack of 1mm2 dice would certainly have lower yields than 100 wafers of 100mm2 integrated circuits. In reality, the optimal number of stacks depends on evenly dividing integrated circuits, and the yield of the attachment process.

Figure 9 – Yield impact of wafer to wafer bonding

Die to die bonding stacks known good quality dice together; ensuring manufacturing yield is controlled at a sufficiently high level before attachment. The manufacturing throughput is reduced since individual die are processed rather than whole wafers. However, the yields are higher than wafer to wafer bonding. In the example in Figure 9, a two layer stack with 2 defects per wafer produced 24 out of 28 good stacks, for wafer to wafer bonding. Assuming the same situation, die to die bonding would have even better yields, 26 out of 28 good stacks.

The overall impact of 3D integration is that the sweet spot for integrated circuits is likely to change a bit. Executives from Intel and AMD have noted that generally, 100-160mm2 is ideal for high volume microprocessors. With 3D integration, the sweet spot is likely to change to 50-80mm2 for two layer stacks, or 33-53mm2 for a three layer stack, etc. The overall area for integrated circuits will probably stay the same or slightly increase, but the area for a given layer will decrease substantially.

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