New compute efficiency data shows GPUs with a clear edge over CPUs, but the gap is narrowing as CPUs adopt wide vectors (e.g. AVX). Surprisingly, a throughput CPU is the most energy efficient processor, offering hope for future architectures. Our data also shows some advantages of AMD’s Bulldozer, and the overhead associated with highly scalable server CPUs.
IBM’s mainframes are the oldest line of computers, dating back to 1964 and occupy a special place as the world’s first instruction set architecture. This longevity and extreme backwards compatibility are responsible for perhaps the most lucrative computer franchise. IBM’s z196 is the first mainframe with an out-of-order CMOS microprocessor, and also the first with an integrated L3 cache. These two innovations are largely responsible for a 30-40% improvement in performance over the previous generation z10.
Larrabee is Intel’s unique architecture for a family of throughput processors, developed for the graphics and HPC markets. We have recently learned that graphics products based on Larrabee 1, the first implementation, have been canceled and that it will instead be used as a software development vehicle. Larrabee’s troubles lay in software, and now the question is what lies ahead in the future for Larrabee and Intel’s graphics products.
David Kanter discusses 32nm process technologies presented at IEDM 2008 and VLSI 2009, including a discussion of high-k dielectrics and metal gates, immersion lithography and double patterning. Results from key manufacturers such as Intel, IBM/AMD, TSMC, Toshiba and others are discussed, analyzed and compared against previous generations using metrics for density (logic and SRAM) and switching speed metrics (for NFETs and PFETs).
Intel’s eagerly Nehalem microarchitecture is a tremendous advance over the previous generation, pushing forward both system integration and core performance. Nehalem includes 4 cores with simultaneous multi-threading, an integrated memory controller, the new CSI (or QPI) coherency links and a redesigned cache hierarchy in a single die. The first 55xx series Xeons, based on Nehalem will come to market shortly, and with that in mind, we take a look at the performance and power efficiency advantages for Nehalem.
Learn the details on Intel’s 45nm Nehalem processor, which features an new system interface: DDR3 integrated memory controllers and CSI or QuickPath Interconnects. The Penryn/Core microarchitecture has been substantially upgraded with improvements spanning the whole pipeline, especially notable is the addition of simultaneous multithreading, a new three level inclusive cache hierarchy and TLBs, an improved loop cache and subtle refinements to almost every other major section of the design.
In this article David Wang takes a look at the 45nm shrink of the CELL microprocessor, which was presented at ISSCC 2008. He discusses the design trade-offs made in porting CELL to 45nm and the results achieve in terms of power and die size relative to earlier versions of CELL.
David Wang provides an overview of disclosures at IEDM 2007, including presentations from TSMC, Fujitsu, IBM, Toshiba, Sony, AMD, NEC on their 45nm immersion lithography processes and Intel’s 45nm high-K and metal gate process which relies on dry lithography.
This article presents a preview of ISSCC 2008, including discussion of Intel’s Itanium processor, codenamed Tukwila and an ultra-low power x86 MPU codenamed Silverthorne. Other presentations include Sun’s Rock and Niagara 3 processors, the 45nm CELL processor and assorted DRAM and SRAM prsentations.
This article provides a technical overview and a performance preview of Intel’s upcoming Stoakley platform, which uses the 45nm Harpertown server processor and the Seaburg chipset.