Notes on the Montecito Launch

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Introduction On Tuesday, I attended Intel’s launch for the eagerly awaited Itanium MPU known as Montecito. I was also given an opportunity to speak with Kirk Skaugen, the GM of the Server Platforms Group. While there has been pretty good coverage of the event, there has not been much in the way of analysis. Rather […]

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A Preview of Intel’s Bensley Platform (Part II)

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Introduction In our last article, we outlined the architecture of the Bensley platform with the Blackford chipset and compared it with the prior generation platform with the Lindenhurst chipset and Nocona CPU. We also looked at Intel’s estimates for the performance of fully loaded and highly tuned systems. However, few fully loaded systems are purchased, […]

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CELL Microprocessor III

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This is the third article in a series covering the CELL microprocessor, co-developed by IBM, Sony and Toshiba.

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CELL Microprocessor Revisited

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Why? Details on the CELL processor, designed by the collective efforts of Sony, Toshiba and IBM (STI), were previously disclosed at ISSCC 2005. The previous article provided coverage of the hardware details of the CELL processor, based on the information made available at ISSCC 2005. The purpose of this article is to act as a […]

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ISSCC 2005: The CELL Microprocessor

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This article is an overview of the CELL microprocessor as presented at ISSCC 2005 by IBM, Toshiba and Sony.

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Sizing up the Super Heavyweights

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In this Silicon Insider, Paul examines the current, and near future, incarnations of the two server architectures vying for the performance crown: IBM’s POWER and Intel’s IPF.

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Coverage of IEDM 2003: AMD and Intel on Day 2

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Partial coverage of IEDM 2003 Day 2, focusing on AMD and Intel process technologies

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