The Players

Among the four companies, AMD's road map, as presented at the Microprocessor Forum, outlined the most technically optimistic plans.

AMD described the K6 3D, a chip scheduled to roll out in the first half of 1998. Designed with a 100-MHz bus and 100-MHz interface to L2 cache, the chip adds 24 instructions to a superscalar MMX unit. In addition, the K6 + 3D, to be introduced in the second half of 1998, includes a full-speed L2 cache that is actually embedded in the chip.

As for AMD's K7, scheduled for 1999, AMD said the device will use the EV-6 bus protocol of the Alpha chip from Digital Equipment Corp. In addition, the chip will be shipped in a module interchangeable with Intel's Slot 1 module, code-named Slot A.

Cyrix plans similar enhancements to its 686MX architecture. Cyrix will heat things up in late 1998 with the introduction of a processor, code-named Cayenne, that addresses a long-standing criticism of Cyrix processors-- floating point performance. Cyrix will also add 15 instructions to what it calls the MMX floating-point unit, a dual-issue/dual-execute unit that supposedly matches Intel's in MMX performance

The processor, based on the 6X86MX core, has a dual issue, pipelined floating point unit to improve 3-D graphics, DVD, and 3-D audio applications. In essence, the architecture will let the chip perform two single-precision floating- point operands in parallel, enabling performance of four floating point operations/seer per clock cycle. It also has 64KB of Level 1 cache and will be built on a 0.25 micron process. Scheduled for production in the second half of 1998, the chip will perform at an equivalent of Intel's Pentium II architecture running at 300 MHz to 400 MHz.

Centaur's C6 processor, now shipping, has obtained Windows 95 compatibility. In the second half of 1998, Centaur's C6+ will add an integrated 256-Kbit L2 cache, with a process shrink to 0.25 micron. Centaur Technology has changed its architecture by implementing superscalar MMX pairing to attain, decode, issue, and execute two instructions per clock. It has also redesigned its floating-point unit to be fully pipelined. To speed geometry processing, Centaur has added 53 new X86 instructions (amounting to 12 opcodes) and 22 floating-point registers. The company's WinChip C6+ processor is scheduled for tape-out in mid-November and is slated to begin shipping in the second quarter of 1998.

As for IBM, they are content to follow the leader who they seem to believe is AMD.

Socket-7 or Slot-1 in 1998?

Despite declarations on the longevity, feasibility, and expandability of the socket 7 design, AMD and Cyrix are hedging their bets. Both AMD and Cyrix indicated they are looking into a slot design for future generations, perhaps as early as 1998.

Cyrix went so far as to state that they will determine by early 1998 if the channel is more in favor of a slot or a socket design and will produce CPUs based on the Cayenne core according to market demand. Cyrix is claiming that its merger with National Semiconductor will give it access to much of the highly guarded intellectual property surrounding the Pentium II through a National licensing agreement that predates the existence of the chip itself.

Cyrix has said that a shift to Slot 1 is feasible, but would not confirm whether the company has decided to move in that direction.

The Risk

Determined to blaze their own trails and create their own opportunities, the microprocessor rivals gave notice that they're no longer content to follow Intel's lead and they are striking out on their own. Unfortunately, they are all charging off in different directions.

Alternative CPU makers are attempting to boost the graphics performance of future processors by putting their own spin on the MMX instruction set instead of waiting on the sidelines for Intel to come out with their technology. Unfortunately each vendor outlined a different and incompatible set of multimedia instructions to be added to their forthcoming microprocessors. The lack of a uniform instruction set to speed up 3-D applications, however, may ultimately prove to be a bad idea.

The variety of proprietary instruction sets creates potential for extensions that are all incompatible. These incompatibilities cause more work for developers whose software must accommodate each specification to run on all systems. Software developers may ultimately resist the moves and opt not to develop for the alternative platforms. By trying to control their own destiny, there is a chance that they may be cutting their own throat.

Conclusion

Processor makers are drawing lines in the sand to designate where in the market they are going to play. While AMD is going head-to-head with Intel, positioning its products as an alternative to Intel, Cyrix's Cayenne processor is being marketed as a core, in anticipation of the company's acquisition by National Semiconductor Corp. Cyrix with its merger with National Semiconductor nearly complete, will continue to funnel its efforts toward the mid and low-range of the market. In the low end, Cyrix now has to compete with Centaur as it begins shipping its first generation processors.

The innovation in these new chips is impressive, but it shows there is little coordination among the x86 vendors. Although all four companies hinted at a common initiative to standardize on a 100-MHz bus, they spent the majority of their time pushing their own agenda. This is truly disappointing. If the alternative CPU makers had worked together this mess could have been avoided.

In my opinion, the AMD initiative is bold, but I question how much of it they can actually deliver. AMD CEO Jerry Sanders is notorious for overpromising and underdelivering. Cyrix's Cayenne doesn't excite me. However, I am glad that Cyrix realizes that it is extremely important that to resolve the relatively low floating point performance that has dogged its CPUs. Centaur is going after the low end and as I have said in the past, I don't care about this segment of the CPU market.

Given the fact the that alternative CPU makers have finally turned their sights on each other and started fighting it out in the socket 7 arena, I am sure that Intel CEO Andy Grove will be sleeping better at night.

It will be very interesting to see how much of what was said at the 1997 Microprocessor Forum will actually come to fruition in 1998.

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