In this article David Wang takes a look at the 45nm shrink of the CELL microprocessor, which was presented at ISSCC 2008. He discusses the design trade-offs made in porting CELL to 45nm and the results achieve in terms of power and die size relative to earlier versions of CELL.
David Wang provides an overview of disclosures at IEDM 2007, including presentations from TSMC, Fujitsu, IBM, Toshiba, Sony, AMD, NEC on their 45nm immersion lithography processes and Intel’s 45nm high-K and metal gate process which relies on dry lithography.
Introduction The 2005 International Electron Devices Meeting (IEDM) was held in the Hilton Hotel on Connecticut Ave in Washington DC from December 4 through December 7. In the four day period, 1800 attendees from all over the world listened to and examined materials presented on the state of the art in the field of semiconductor [...]
This is the third article in a series covering the CELL microprocessor, co-developed by IBM, Sony and Toshiba.
Why? Details on the CELL processor, designed by the collective efforts of Sony, Toshiba and IBM (STI), were previously disclosed at ISSCC 2005. The previous article provided coverage of the hardware details of the CELL processor, based on the information made available at ISSCC 2005. The purpose of this article is to act as a [...]
This article is an overview of the CELL microprocessor as presented at ISSCC 2005 by IBM, Toshiba and Sony.
In part 2, David discusses reasons for memory errors and expected rates
David Wang provides an overview of error correction schemes for modern DRAM devices
Partial coverage of IEDM 2003 Day 2, focusing on AMD and Intel process technologies