3D Integration: A Revolution in Design

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The continuing pace of chip level feature miniaturization – Moore’s Law – has resulted in the doubling of the number of transistors per unit area approximately every couple of years. Chip designers have been provided with a plethora of transistor options to choose from in order to optimize for a given constraint. New materials with higher dielectric constants such as hafnium-based high-k gate oxide materials, along with metal gate electrodes, decrease leakage and boost drive current. Strained silicon engineering enables higher transistor switching speeds. Different transistor designs featuring multiple threshold voltages optimize for low power or high performance applications.

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