The Looming Battle in 64 Bit Land

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MIPS: From Intel Challenger to Super Mario

Like PA-RISC and SPARC, the highly respected MIPS architecture can trace its roots back to the earliest days of the RISC revolution. In fact, MIPS was so highly regarded that Compaq, Microsoft, DEC, and MIPS Technologies Inc. formed the Advanced Computing Environment (ACE) consortium in 1991, an initiative that once posed a credible threat to overthrow Intel’s x86 hegemony on the PC desktop and replace it with MIPS processors. After some financial difficulties following the collapse of the ACE consortium in 1992 (from a combination of internal strife and Intel’s heavy handed tactics in Asia to keep motherboard makers from supporting ACE) MIPS Technologies was acquired by Silicon Graphics Inc. (SGI). Around this time MIPS was able to deliver the first commercial true 64-bit microprocessor, the R4000. The R4000 was followed up by the slightly improved R4400. In 1995 the advanced, out-of-order execution, 0.35 um MIPS R10000 (R10K) core shipped at clock rates up to 200 MHz.

During the 1990’s low end 32 and 64 bit implementations of the MIPS ISA became very popular for embedded control applications. The success of the 64 bit R4300 processor in the Nintendo 64 video game console helped MIPS to recently achieve the milestone of first RISC microprocessor architecture to sell over 100 million units. Unfortunately this success wasn’t mirrored on the high-end. In1997 SGI canceled plans for new MIPS processor cores code named H1 and H2 and announced it would adopt IA-64. Subsequent delays to Merced/Itanium have left SGI vulnerable to its competitors because, unlike HP for example, SGI didn’t keep its R10K and R12K processors competitive in clock frequency. The recent disclosure of respectable SPEC2000 benchmark scores for the 400 MHz R12K underlines the perpetual heroic efforts at system and compiler level tweaking at SGI to make up for the shortcomings of their semiconductor manufacturing partners. Ironically the MIPS Technology subsidiary of SGI is being gradually spun out of SGI to further exploit its successes in the embedded control market even as its parent continues to suffer.

SGI has announced it would continue work on its own continued tweaks of the basic R10K core. The R14K is targeting a 400 to 450 MHz clock rate with an improved system interface. The R16K should follow next year with L1 caches doubled in size (to 64 Kbyte each) will run in the 600-800 MHz range. A decision for a further shrink of the R10K core into a R18K device will be made at a future date. Presumably the R18K’s fate will depend on the degree of market acceptance of IA-64 based products. But none of these new devices are likely to do much to slow the MIPS ISA’s full retreat from general purpose computing.

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