ISSCC 2005: The CELL Microprocessor

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SPE Pipeline

Figure 6 – SPE pipeline diagram

Table 1 – Unit latencies for SPE instructions.

Figure 6 shows the pipeline diagram of the SPE and Table 1 shows the unit latency of the SPE. Figure 6 shows that the SPE pipeline makes heavy use of the forward-and-delay concept to avoid the access latency of a register file access in the case of dependent instructions that flow through the pipeline in rapid succession.

One interesting aspect of the floating point pipeline is that the same arrays are used for floating point computation as well as integer multiplication. As a result, integer multiplies are sent to the floating point pipeline, and the floating point pipeline bypasses the FP handling and computes the integer multiply.

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