On the eve of the 50th anniversary of Moore’s Law, the future of silicon CMOS is an open question. With rising costs and uncertain benefits, some semiconductor companies have questioned the wisdom of pursuing further scaling. I predict that Intel’s 10nm process technology will use Quantum Well FETs (QWFETs) with a 3D fin geometry, InGaAs for the NFET channel, and strained Germanium for the PFET channel, enabling lower voltage and more energy efficient transistors in 2016, and the rest of the industry will follow suit at the 7nm node.
My favorite paper from the ISSCC processor session describes an adaptive clocking technique implemented in AMD’s 28nm Steamroller core that compensates for power supply noise. Initial results show a 10-20% decrease in power consumption from reducing the voltage, with no loss in performance. This elegant technique is likely to be adopted across AMD’s entire product line including GPUs, x86 CPUs, ARM-based CPUs, and other critical blocks in highly integrated SoCs.
The 14nm Knights Landing leverages Intel’s resources with a laser-like focus on HPC to deliver a massive improvement over the previous generation. The building block of this architecture is a pair of Silvermont-inspired CPUs with wide vector units and most importantly, a brand new cache hierarchy, on-die fabric, and system infrastructure that is shared with Skylake. This article is an in-depth analysis and prediction of the Knights Landing architecture.
Knights Landing is Intel’s first clean sheet redesign of the Larrabee family, targeted at throughput computing and manufactured on a 14nm process with products expected in late 2014 or early 2015. The adoption of AVX3, on-package embedded DRAM, and bootable products have been disclosed, but most details are unknown. This article analyzes the options available for the Knights Landing CPU core and explains why Intel’s existing cores are a poor fit for the target workloads, concluding that the most likely outcome is a new custom core for Knights Landing.
Silvermont is Intel’s first CPU core tailored for power efficient applications such as smartphones, tablets, and microservers. The 22nm microarchitecture features updated instruction set extensions, full out-of-order execution with a tightly coupled L2 cache, aggressive power management, and a new high performance SoC fabric. These enhancements deliver tremendous performance and frequency gains over the aging Atom core, putting Intel’s mobile strategy in a more competitive position.
Graphics is a focal point of the upcoming Haswell platform, necessitating a high bandwidth memory solution. To deliver high performance Intel is returning to the DRAM market, which it exited in 1985. The memory that ships with Haswell will be a custom embedded DRAM mounted in the package and manufactured on a variant of Intel’s 22nm process. By avoiding the commodity memory market, Intel will preserve high margins by cannibalizing discrete GPUs and dedicated graphics memory.
The server market is at a potential inflection point, with a new breed of ARM-based microserver vendors challenging the status quo, particularly for cloud computing. We survey 20 modern processors to understand the options for alternative architectures. To achieve disruptive performance, microserver vendors must deeply specialize in particular workloads. However, there is a trade-off between differentiation and market breadth. As the handful of microserver startups are culled to 1-2 viable vendors, only the companies which deliver compelling advantages to significant markets will survive.
The iPad 3 was an influential and successful tablet, but an excellent example of an unbalanced system. In particular, the superb Retina display was not adequately matched by the GPU of the A5X, and represented a step backwards in terms of graphics capabilities. This article explores the challenges of designing innovative products given the underlying technical constraints, through the lens of the iPad 3 and its successors.
Near-threshold voltage computing extends the voltage scaling associated with Moore’s Law and dramatically improves power and energy efficiency. The technology is superb for throughput, at the cost of latency, and best suited to Intel’s products for HPC and mobile graphics.
The new ARMv8 architecture is classically British; a clean and elegant 64-bit instruction set, with compatibility for 32-bit software. The 64-bit mode eliminates many complicated and awkward features and will foster a larger and more diverse ARM ecosystem with new licensees and applications.