Nvidia’s Kal-El sports a novel 5th ‘companion’ core to lower idle power. We look at the trade-offs and benefits to this approach and explain why it will be a strong tablet SoC, but only an incremental gain for smartphones.
AMD’s Hot Chips presentation delved into Llano, the first mainstream Fusion product, with details and results for power management. Previous disclosures painted a poor picture, which is far from the truth. Given the older CPU and GPU designs and time-to-market pressure, the results are quite good. Llano’s power management focuses on the most important aspects and is a solid foundation for future generations that will be much more power aware and optimized.
Enthusiasts and engineers know cooling is vital; it raises frequency and dramatically lowers power by reducing CPU or GPU temperatures. The world’s fastest supercomputer shows that thermal management can increase CPU performance/watt by 20% and cooling is critical for 3D integration and Moore’s Law.
For over 40 years, the planar transistor has been the keystone of the semiconductor industry. Intel’s new 22nm tri-gate transistor is revolutionary, moving transistors into a three dimensional world. After 10 years of research, this novel structure is the next step for Moore’s Law and promises to substantially improve performance and power efficiency.
Intel’s Sandy Bridge ISSCC paper discusses a number of challenges they will eventually impact most vendors. The novel architectural choices and circuit design solutions that they describe give insight into current and future products from Intel, but also the general direction of the industry. The overarching theme is taking advantage of Moore’s Law at 32nm and beyond, which entails considerable attention to design complexity, process variation, power efficiency and validation.
As Moore’s Law continues, each new generation of semiconductor manufacturing is ushered in by new challenges, hurdles and solutions. At ISSCC 2011, a panel with speakers from Global Foundries, IBM, Intel, Renesas and TSMC discussed manufacturing and circuit design interactions at the upcoming 22nm node. Industry leaders have reached a broad technical consensus, although with several subtle differences. This report explores the key challenges and solutions at 22nm; focusing on variation and co-optimization between design and manufacturing. As a result of the needed collaboration, understanding of physical design and manufacturing is even more critical to cutting edge chip development and achieving good performance, power and yields.
The integration predicted by Moore’s Law is fundamentally driven by advances in semiconductor manufacturing. One of the key challenges is scaling to ever finer and denser geometries, while improving the performance of transistors. IEDM and the VLSI Symposium are the premier venues to discuss the challenges and opportunities for future process technologies. No commercial 22nm process technologies were presented at IEDM 2010, but in the last two years a number of advances have been disclosed, both for high performance and low power applications. This article describes several 32nm and 28nm nodes from Intel, IBM’s Common Platform and TSMC, plus novel applications such as IBM’s 32nm eDRAM that have been disclosed at IEDM and VLSI.
Intel recently announced they would manufacture 22nm FPGA’s for Achronix, a small start up. Intel’s process technology and fabs are the heart of the company. Opening up to third parties is a tremendous departure from the status quo – one that surprised and perplexed many people. Our analysis explores three possible explanations and infers that Intel is enabling complementary technologies rather than entering the foundry business.
The computer industry is on the cusp of yet another turn of the Wheel of Reincarnation, with the graphics processor unit (GPU) cast as the heir apparent of the floating point co-processors of days long gone. Modern GPUs are ostensibly higher performance and more power efficient than CPUs for their target workload, and many companies and media outlets claim they are leaving CPUs in the dust. Is this really the case though? This article explores the quantitative basis for these claims, with some surprising results.
David Kanter discusses 32nm process technologies presented at IEDM 2008 and VLSI 2009, including a discussion of high-k dielectrics and metal gates, immersion lithography and double patterning. Results from key manufacturers such as Intel, IBM/AMD, TSMC, Toshiba and others are discussed, analyzed and compared against previous generations using metrics for density (logic and SRAM) and switching speed metrics (for NFETs and PFETs).