Testing the Limits of CPUs

It has been suggested by some that any of the current batch of processors can run at 100MHz bus speed, were it not for the limitations of the L1 cache. This tends to contradict the observations we have made, which we have made public. Our statement was that inherent limitations in design and materials would prevent most 66MHz processors from operating at 100MHz bus speed. Timing issues and the inability of the CPU’s transistors to operate fast enough were our contention. Several, purportedly knowledgable indiviuals, disagreed and said that it is only the L1 cache that causes any timing problems, so we decided to test the theory out. In doing so, we found that processors do indeed have their limits regarding the bus speed, though L1/L2 cache also may have some effect.

In order to test these limitations, we used an M Tech R581A for Socket 7 processors, and an AX6B for Slot 1 processors. While the R581A does not have an ‘official’ 100MHz bus speed, it will run with certain processors if the L2 cache is disabled. We decided to begin our Socket 7 testing at 90MHz, which is a stable bus speed for the R581A. The AX6B has a fully functioning 100MHz bus speed, so we used that to test our Slot I processors.

Rather than test every single processor, we chose several that had a chance to make 100MHz, and several that we didn’t think had a chance. For Socket 7, we chose an Intel Classic P150, Intel MMX P166, AMD K6-233 and Cyrix 6x86MX PR200. For Slot 1 testing we chose the 233MHz and 300MHz processors.

In order to verify our tests, we booted each processor at it’s officially specified bus speed and multipler to ensure it would operate properly. Next, we bumped up the bus speed and adjusted the multiplier so the CPU would be operating as closely to it’s specified MHz rating as possible, either faster or slower, so that our tests would not fail merely due to the overall clock speed being faster than the processor can handle.

Socket 7 Limitations

The first processor we tested was the Cyrix 6x86MX PR200, which has a rated speed of 166MHz. At 2.0 x 90MHz, the CPU would boot into Windows, however at either 1.5 x 100MHz or 2.0 x 100MHz we could not get the board to even POST. A POST card indicates that the POST routine does not even start, which indicates that the processor is inoperable at either of these settings. The test was performed a second time with both L1 and L2 cache disabled to eliminate cache memory timing problems as the culprit, with the same results.

We next tried the Intel Classic Pentium 150MHz processor. While the CPU worked flawlessly at it’s rated speed (2.5 x 60MHz), it would hang during POST at 2 x 90MHz, even if either L1 or L2 cache were disabled. Only by disabling *both* L1 and L2 cache would the processor complete the POST routine and boot into Windows. When we tried the 100MHz settings (both 1.5x and 2.0x), we got the same results as with the 6x86MX processor – no POST at all regardless of the cache settings.

Since we had previously attempted to run our Intel Pentium 166MHz w/MMX at 100MHz during our verification tests of the R581A motherboard several weeks ago, we expected to fail with this processor as well. At 2.0 x 90MHz, the processor booted straight into Windows with both L1 and L2 cache enabled, indicating that it was better able to handle the faster bus speeds than the Classic Pentium. At 2.0 x 100MHz, the CPU failed to POST at all, just as the two previous processors had.

The AMD K6-233 was the first processor we tried that would actually start the POST routine at 100MHz. With either L1 or L2 cache enabled, only the video would be initialized and the system would hang after the initial splash screen. When we disabled cache options, the system would run through the memory check, but hang before initializing the devices and assigning IRQs.

The conclusion we have come to is that processors do indeed have limitations regarding operation at 100MHz, even without cache issues being involved. Without L1 and L2 cache, all of the processors showed some improvement at either 90MHz or 100MHz operation, all of them exhibited timing problems or inability to operate as the bus speeds increased. Since we had previously run the R581A successfully at 100MHz with 50ns EDO and a K6-266, the problem was not with the memory or motherboard, but had to be the CPUs.

Slot 1 at 100MHz

The two Slot 1 tests were much more interesting than the Socket 7 tests. Both the 233MHz and the 300MHz processors booted and ran flawlessly at 100MHz, proving that the Pentium II processors were designed to operate at much faster speeds than their Socket 7 cousins.

The PII 233MHZ ran without any problems at speeds as high as 3.0 x 103MHz using aggressive memory timings. At 112MHz, the processor simply would not operate properly, hanging partway through POST. At 133MHz, the system simply would not POST, suggesting that the limitation of the PII processors is somewhere between 112MHz and 133MHz.

The PII 300MHz would run even at 3.0 x 112MHz, though the memory timings had to be slowed down. This processor also failed to POST at 133MHz settings. One item of interest is that while the 233MHz processor could be pushed approximately more than 33% faster than it’s rated speed, the 300MHz processor was limited to less than a 20% ‘push’. No matter what settings we tried, the processor simply would not operate reliabily at any speed beyond 350MHz. Even at 4.5 x 83.3MHz, the board would hang during POST (though it would run at 4 x 83.3MHz). Either Intel has figured out how to limit the overall speed of the processor, or the design limitations are being reached at those speeds.


Based upon the facts that we recorded, it seems fairly conclusive that not all processors will work at 100MHz bus speed, as we had reported in our report several weeks ago. We also determined that L1 cache speed has little to do with the ability of the processor to operate at the faster bus speeds. In fact, unless both L1 and L2 cache were disabled, there was almost no difference in the ability of the processor to handle the faster bus speeds and even with both disabled there was only a marginal improvement.

The symptoms we observed suggested both inability of the processor circuitry to operate at higher speeds (no POST), or timing problems (hanging during POST or Windows initialization). These problems were encountered even at a known functioning bus speed of 90MHz on some processors. We therefore are still convinced that timing problems are not limited to memory (L1/L2 cache and system RAM), and that most current Socket 7 processors simply will not operate at 100MHz, even if a fully capable 100MHz motherboard were available.

The only real surprise we received was that it seems that *all* Pentium II processors can operate at 100MHz bus speeds. Unfortunately, our tests did not include a processor that *officially* supports 100MHz, so we could not make any determination as to whether these would be able to handle the 112MHz bus speeds any better.

Be the first to discuss this article!