For 4 years, Intel has struggled to move into the market for mobile devices. Conventional wisdom holds that x86 is too inefficient for smart phones. The recently announced 32nm Medfield proves that x86 is a viable option and that Intel can design smart phone products. We explore the Medfield SoC and analyze the impact on Intel’s mobile strategy.
IBM z196 Mainframe Architecture
January 3, 2012 by
IBM’s mainframes are the oldest line of computers, dating back to 1964 and occupy a special place as the world’s first instruction set architecture. This longevity and extreme backwards compatibility are responsible for perhaps the most lucrative computer franchise. IBM’s z196 is the first mainframe with an out-of-order CMOS microprocessor, and also the first with an integrated L3 cache. These two innovations are largely responsible for a 30-40% improvement in performance over the previous generation z10.
ISSCC 2012 Preview
November 28, 2011 by
Highlights of the upcoming 2012 ISSCC include the first 22nm disclosures from Intel and several SoC papers from AMD, Cavium Networks and Oracle. Looking out further to the future, the clear focus is power consumption. There are several papers from Intel on low-power logic, one from IBM discussing 3D integration of embedded DRAM and a third from Fujitsu on system level power for the K supercomputer.
Nvidia’s Kal-El Goes Asymmetric
October 5, 2011 by
Nvidia’s Kal-El sports a novel 5th ‘companion’ core to lower idle power. We look at the trade-offs and benefits to this approach and explain why it will be a strong tablet SoC, but only an incremental gain for smartphones.
Llano at Hot Chips
August 31, 2011 by
AMD’s Hot Chips presentation delved into Llano, the first mainstream Fusion product, with details and results for power management. Previous disclosures painted a poor picture, which is far from the truth. Given the older CPU and GPU designs and time-to-market pressure, the results are quite good. Llano’s power management focuses on the most important aspects and is a solid foundation for future generations that will be much more power aware and optimized.
Sandy Bridge for Servers
July 28, 2011 by
Intel’s Sandy Bridge-EP arrives late this year to take on AMD’s Bulldozer in 2 and 4-socket servers. It offers up to 8 cores with a new system architecture including 20MB L3 cache, 4 DDR3 memory controllers and faster 8GT/s QPI 1.1 links. Sandy Bridge-EP is also the first server CPU to integrate PCI-E 3.0 on-die, with up to 40 lanes – a significant bandwidth and power efficiency advantage. This article compares the system architecture and design to previous approaches and shows that Sandy Bridge-EP will be a compelling upgrade for 2-socket servers and attractive for certain 4-socket systems, particularly those with large I/O needs.
Intel’s Quick Path Evolved
July 20, 2011 by
Intel’s Quick Path Interconnect (QPI) was a massive step forward over the front-side bus that was used from 1995-2008. QPI finally caught up and exceeded AMD’s HyperTransport, helping Intel retake much of the server market. The next generation QPI 1.1 was re-architected based on trends and changes in the computer industry. QPI 1.1 is an incremental improvement at the physical and logical layer, but a substantial change in the coherency protocol. Sandy Bridge-EP will be the first product to implement QPI 1.1, later this year.
What Do Overclockers and Supercomputers Have in Common?
June 20, 2011 by
Enthusiasts and engineers know cooling is vital; it raises frequency and dramatically lowers power by reducing CPU or GPU temperatures. The world’s fastest supercomputer shows that thermal management can increase CPU performance/watt by 20% and cooling is critical for 3D integration and Moore’s Law.
Poulson: The Future of Itanium Servers
May 18, 2011 by
Over a decade, Itanium scaled down to 65nm re-using the same basic design. The new 32nm Poulson architecture moves from static VLIW to a more conventional pipeline. It has a new core with dynamic scheduling, fine-grained multithreading and a shared L3 cache. The net result is a vastly more efficient microprocessor that should achieve 2.5-2.8X higher performance and power high-end servers for the next 10 years.
Sandy Bridge ISSCC Update
April 20, 2011 by
Intel’s Sandy Bridge ISSCC paper discusses a number of challenges they will eventually impact most vendors. The novel architectural choices and circuit design solutions that they describe give insight into current and future products from Intel, but also the general direction of the industry. The overarching theme is taking advantage of Moore’s Law at 32nm and beyond, which entails considerable attention to design complexity, process variation, power efficiency and validation.
