Intel’s EPIC Striptease Continues

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Battle of the Acronyms

If you have picked up a high tech magazine or business newspaper in the last three years you are probably already aware that Merced is the code name for a future Intel chip. Named after a river 75 miles east of silicon valley, Merced is the first implementation of IA-64, an interesting new computer instruction set architecture (ISA) co-developed by Intel and Hewlett Packard. IA-64 is a 64-bit reduced instruction set computing (RISC) design with a handful of new and unproved features added in. In fact, Intel and HP think these new features are so significant that IA-64 requires an entirely new category of computer architecture to encompass it. To fill this need the acronym EPIC (which stands for Explicitly Parallel Instruction Computing) was coined.

It is clear that IA-64 is distinct in many ways from the existing group of RISC architectures (which include MIPS, SPARC, PA-RISC, PowerPC, and Alpha) which were all designed roughly around the same time (in the mid to late 80’s). But IA-64 and those RISC ISAs were designed with the same purpose in mind – to simplify and streamline the hardware to permit higher performance at the cost of putting a larger burden on the compilers to generate and schedule correct and efficient machine code. Also, many of the IA-64 features promoted by Intel, such as predication and explicit encoding of program parallelism within instructions, have been incorporated in RISC designs in the past. So it is quite debatable whether or not it merits a new phylum of its own in computer design classification.

Official Name Revealed but Little Else

Merced has attracted an inordinate amount of attention for an unreleased chip for several reasons. It is the first microprocessor based upon an unproved and controversial new architecture. It is also Intel’s first 64-bit architecture and it represents the first major change to the their mainstream ISA since x86 went 32-bit with the 80386. Also, several companies, SGI and HP, have announced that they will eventually jettison their own proprietary RISC processor designs and adopt the Merced and follow-up IA-64 processors from Intel in their place. Finally, the myth of Merced has been inflated by Intel’s habit of making grandiose claims of future performance dominance by IA-64 over existing RISC families while revealing very little hard information about Merced and even less about future IA-64 processors.

At this year’s Microprocessor Forum held last week in San Jose, Intel received the double time slot it requested to provide new details about the inner workings of Merced. However, considering how little actual new information Intel released perhaps half a time slot would have been more appropriate. Probably the most interesting and newsworthy fact revealed was that Merced will be officially marketed under the name “Itanium”. Intel understands the importance of product branding and how successful it was in associating the name Pentium with fast and reliable computing hardware in the minds of PC buying individuals and corporations. No doubt we can expect McKinley and Madison to eventually shed their code names in favor of Itanium II and III or perhaps Bitanium and Tritanium.

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