Design Challenges at 22nm Article

Article: 22nm Design Challenges at ISSCC 2011
By: David Kanter (dkanter.delete@this.realworldtech.com), March 14, 2011 12:36 am
Room: Moderated Discussions
As Moore's Law continues, each new generation of semiconductor manufacturing is ushered in by new challenges, hurdles and solutions. At ISSCC 2011, a panel with speakers from Global Foundries, IBM, Intel, Renesas and TSMC discussed manufacturing and circuit design interactions at the upcoming 22nm node. Industry leaders have reached a broad technical consensus, although with several subtle differences. This report explores the key challenges and solutions at 22nm; focusing on variation and co-optimization between design and manufacturing. As a result of the needed collaboration, understanding of physical design and manufacturing is even more critical to cutting edge chip development and achieving good performance, power and yields.

http://www.realworldtech.com/page.cfm?ArticleID=RWT031411013528

As always, comments and feedback are welcome.

David
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Design Challenges at 22nm ArticleDavid Kanter03/14/11 12:36 AM
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