Sandy Bridge-EP article online

As one reader pointed out, we omitted mention of the speed of QPI 1.1...but this was for a good cause, saving some juicy tidbits for this week's article.

In this piece, we discuss the system architecture (aka uncore) of the upcoming Sandy Bridge-EP. This includes a discussion of changes to the ring interconnect compared to consumer Sandy Bridge variants. We also examine some of the physical design choices that were described at ISSCC earlier this year, particularly in the area of clock domains.

"Intel's Sandy Bridge-EP arrives late this year to take on AMD's Bulldozer in 2 and 4-socket servers. It offers up to 8 cores with a new system architecture including 20MB L3 cache, 4 DDR3 memory controllers and faster 8GT/s QPI 1.1 links. Sandy Bridge-EP is also the first server CPU to integrate PCI-E 3.0 on-die, with up to 40 lanes - a significant bandwidth and power efficiency advantage.

This article compares the system architecture and design to previous approaches and shows that Sandy Bridge-EP will be a compelling upgrade for 2-socket servers and attractive for certain 4-socket systems, particularly those with large I/O needs."

http://www.realworldtech.com/page.cfm?ArticleID=RWT072811020122

Comments, feedback and suggestions are welcome.

David