On the UltraSPARC T4

Brett (ggtgp@yahoo.com) on 9/27/11 wrote:
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>DaveC (davecuny@gmail.com) on 9/27/11 wrote:
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>>Gabriele Svelto (gabriele.svelto@gmail.com) on 9/27/11 wrote:
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>>>Whilst Oracle has announced the UltraSPARC T4 with the usual barrage of more or
>>>less canned PR statements and press releases I haven't yet seen much technical
>>>analysis of it so I did a quick wrap-up of it with what is on the internet.
>>>
>>>The UltraSPARC T4 has 8 dual-issue cores, running at 2.85GHz or 3GHz and
>>>supporting speculative out-of-order execution. Each of the cores supports
>>>8 hardware threads, has 16 KiB of L1 I-cache and D-cache and a 128 KiB L2 cache.
>>>The cores share a 4 MiB, 8-ways banked, 16-ways set associative L3 cache. The
>>>chip die-size is 403 mm² and maximum power consumption is 240W.
>>
>>According to the "Server Architecture" doc, the
>>memory controller and interconnect remain unchanged from the T3 to the T4, so we're
>>just talking about a core & cache change.
>
>With 8 threads it is starting to look like an ATI chip with wavefronts.
>ATI and NVidia have not been able to increase the memory >bandwidth because the chips will melt.

I think you got that backwards in terms of timeline. Niagara I came out in 2005 and Afara was acquired in 2002. That's well before DX10 came out or anyone started designing programmable GPUs.

In some ways, I think you can say that Niagara was the original throughput processor. However, it's really aimed at different workloads - e.g. no vectors.

David