By: EduardoS (no.delete@this.spam.com), April 21, 2012 12:53 pm
Room: Moderated Discussions
anonymous (no@spam.com) on 4/21/12 wrote:
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>The BD AGUs can't actually handle INC/DEC.
>
>The current optimization manual finally shows that.
>
>And it's trivial to test it yourself. :)
Link?
The optimization guide avaliable at AMD website doesn't list any instruction that doesn't depend on EX0 | EX1, no op on AGUs writeback to the register file, neither loads or stores, it is exactly the same as on Llano.
For the next model there are some interesting changes:
1) bextr using AGU, but this is instruction generates two ops, one may use the AGU the other the EX0 | EX1 to final step and writeback.
2) mov reg, reg using AGU, maybe done through a crazy form of mov elimination?
---------------------------
>The BD AGUs can't actually handle INC/DEC.
>
>The current optimization manual finally shows that.
>
>And it's trivial to test it yourself. :)
Link?
The optimization guide avaliable at AMD website doesn't list any instruction that doesn't depend on EX0 | EX1, no op on AGUs writeback to the register file, neither loads or stores, it is exactly the same as on Llano.
For the next model there are some interesting changes:
1) bextr using AGU, but this is instruction generates two ops, one may use the AGU the other the EX0 | EX1 to final step and writeback.
2) mov reg, reg using AGU, maybe done through a crazy form of mov elimination?



