By: hcl64 (mario.smarq.delete@this.gmail.com), April 28, 2012 10:39 pm
Room: Moderated Discussions
David Kanter (dkanter@realworldtech.com) on 4/28/12 wrote:
---------------------------
>hcl64 (mario.smarq@gmail.com) on 4/28/12 wrote:
>---------------------------
>>
>>http://en.wikipedia.org/wiki/Asynchrony
>>
>>" In specific terms of **digital logic** and physical layer of communication, an *asynchronous
>>process does not require a clock signal*, in contrast with synchronous and plesiochronous systems."
>
>Yes, that's the correct definition. In the context of a CPU, two domains are asynchronous
>when there is no specific relationship between the frequencies.
>
>All of the BD module runs at the same frequency. i.e. it's synchronous.
>
>DK
*not require a clock signal*, doesn't it mean precisely that the definition is orthogonal to frequency ? .. that is the clock signal is present but
" asynchrony is synonym of statistical multiplexing, such as in packet mode. *The information transmission may or may not start immediately as requested by sender*, the additional delay being caused by medium congestion. Contrast with example of circuit switched communication, which (once circuit is established) allows immediate start of transfer with a guaranteed bit rate."
From domain to domain requests may or may not start immediately. [fetch is in thread A when decode requests thread B... fetch context switches when fetch finishes to fill thread A IBB and start to serve thread B IBB... any miss in the L1-I (or longer "event" ) and decode immediately switches to thread A in its turn ]
" *Confusingly*, a communication is often *synchronous at the physical layer*, while being *asynchronous at the data link layer.* "
Only AMD could clarify, cause it seems both can happen at the same time
---------------------------
>hcl64 (mario.smarq@gmail.com) on 4/28/12 wrote:
>---------------------------
>>
>>http://en.wikipedia.org/wiki/Asynchrony
>>
>>" In specific terms of **digital logic** and physical layer of communication, an *asynchronous
>>process does not require a clock signal*, in contrast with synchronous and plesiochronous systems."
>
>Yes, that's the correct definition. In the context of a CPU, two domains are asynchronous
>when there is no specific relationship between the frequencies.
>
>All of the BD module runs at the same frequency. i.e. it's synchronous.
>
>DK
*not require a clock signal*, doesn't it mean precisely that the definition is orthogonal to frequency ? .. that is the clock signal is present but
" asynchrony is synonym of statistical multiplexing, such as in packet mode. *The information transmission may or may not start immediately as requested by sender*, the additional delay being caused by medium congestion. Contrast with example of circuit switched communication, which (once circuit is established) allows immediate start of transfer with a guaranteed bit rate."
From domain to domain requests may or may not start immediately. [fetch is in thread A when decode requests thread B... fetch context switches when fetch finishes to fill thread A IBB and start to serve thread B IBB... any miss in the L1-I (or longer "event" ) and decode immediately switches to thread A in its turn ]
" *Confusingly*, a communication is often *synchronous at the physical layer*, while being *asynchronous at the data link layer.* "
Only AMD could clarify, cause it seems both can happen at the same time
