By: Eric (lol.delete@this.safetymail.info), April 23, 2012 7:30 pm
Room: Moderated Discussions
EduardoS (no@spam.com) on 4/23/12 wrote:
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>Eric (lol@safetymail.info) on 4/23/12 wrote:
>---------------------------
>>http://news.softpedia.com/news/AMD-s-New-Steamroller-Architecture-to-Bring-Significant-Performance-264918.shtml
>>http://www.xbitlabs.com/news/cpu/display/20120416165428_AMD_Expects_Significant_Performance_Improvements_with_Steamroller_Microprocessors.html
>>
>
>Neither have more information than an old public slide, the first step comes with
>Piledriver stated as 10-15% improvement, and those 10-15% improvement we know will come from:
>- Higher clock due to process maturity and clock mesh;
>- Double L2 write bandwidth;
>- Lower forwarding latency;
>- Slightly bigger instruction window (I'm not sure, IIRC it is just for the FPU scheduller);
>- Other small (or smaller...) changes to the core.
>
>In the Steamroller node there is the same "10-15%" text with a "greater parallelism",
>take your own conclusions to what this does means.
>
Yeah, the +33% figure appears to simply be derived from multiplying +10%-+15% from Bulldozer to Piledriver by +10%-+15% from Piledriver to Steamroller as estimated in that old slide. (At least I couldn't find any other basis for it in either article.) What would be new and very interesting is the information (if accurate) that those performance increase estimates relate to the micro-architecture only, i.e. not including improvements to the clock frequency, caches, memory controller and system architecture. In that case AMD could actually become relevant in the CPU high-end again.
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>Eric (lol@safetymail.info) on 4/23/12 wrote:
>---------------------------
>>http://news.softpedia.com/news/AMD-s-New-Steamroller-Architecture-to-Bring-Significant-Performance-264918.shtml
>>http://www.xbitlabs.com/news/cpu/display/20120416165428_AMD_Expects_Significant_Performance_Improvements_with_Steamroller_Microprocessors.html
>>
>
>Neither have more information than an old public slide, the first step comes with
>Piledriver stated as 10-15% improvement, and those 10-15% improvement we know will come from:
>- Higher clock due to process maturity and clock mesh;
>- Double L2 write bandwidth;
>- Lower forwarding latency;
>- Slightly bigger instruction window (I'm not sure, IIRC it is just for the FPU scheduller);
>- Other small (or smaller...) changes to the core.
>
>In the Steamroller node there is the same "10-15%" text with a "greater parallelism",
>take your own conclusions to what this does means.
>
Yeah, the +33% figure appears to simply be derived from multiplying +10%-+15% from Bulldozer to Piledriver by +10%-+15% from Piledriver to Steamroller as estimated in that old slide. (At least I couldn't find any other basis for it in either article.) What would be new and very interesting is the information (if accurate) that those performance increase estimates relate to the micro-architecture only, i.e. not including improvements to the clock frequency, caches, memory controller and system architecture. In that case AMD could actually become relevant in the CPU high-end again.
