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By: hcl64 (mario.smarq.delete@this.gmail.com), April 28, 2012 11:44 pm

David Kanter (dkanter@realworldtech.com) on 4/28/12 wrote:
---------------------------
>hcl64 (mario.smarq@gmail.com) on 4/28/12 wrote:
>---------------------------
>>David Kanter (dkanter@realworldtech.com) on 4/28/12 wrote:
>>---------------------------
>>Yet the total pipeline length of BD is 15 stages without >the latency hiding effect, so hardly resembling P4.
>
>Do you have any references for that? AMD has never publicly stated the depth, and
>I suspect it's much more like 20 stages.
>

http://www.hardocp.com/article/2011/11/29/hardocp_readers_ask_amd_bulldozer_questions/1

" Mike Butler, Senior Fellow Design Engineer, AMD - The latest architectural advancements from both AMD and our competitors have incorporated advancements from deeper pipelines. The pipeline within our latest "Bulldozer" microarchitecture is *approximately 25 percent deeper* than that of the previous generation architectures. That deeper pipeline is a key technology advancement, providing record breaking frequencies and performance improvements "

GH 12 stages : 12*1.25=15

>>What resembles P4 the most, and most strikingly the Prescott variant, that everybody
>>bashes as being not good and a power hog is IBM z196.
>
>What are you talking about?
>
>>It has proximately the same
>>number of stages(more than 30), is a CISC ISA (perhaps more complex than x86), has
>>complex operand forwarding networks (which can hurt clock >cycle badly) with a
>form of eager execution with >checkpointing
>
>>Its a monster chip with >500mm2 with extensive RAS features(also can hurt clock
>>cycle)... a power hog alright, yet its marketed at 5.2Ghz stock speed, on a 45nm
>>no HKMG SOI process ... i just wonder at *IBM* 22nm FinFET >(HKMG) SOI process!.
>
>It's amazing what you can do with a liquid cooled chip that dissipates 250W.
>

:) just wonder if any chip >500mm2 at 45nm "bulk" no HKMG, could even reach any close to that on *dry ice*...

>>Without wanting to hurt feelings, yes it seems that Intel has the best "bulk" process
>>around bare none today, but perhaps the "marketing gimmicky" of the SOITEC group
>>about SOI offering *up to* 40% better mobility for high >clock high performance chips, is not too much out of place.
>
>LOL. It's off by about a factor of 5X. SOI gives at best a 7% performance advantage
>in 65nm and below. The benefits have consistently diminished over time.
>

Marketing gimmicky perhaps !?, perhaps someone should correct those guys, because something fishingly hot is going on

http://www.soiconsortium.org/corners/fully-depleted-soi/february-2012/index.php

Specially Terence Hook (IBM)
http://www.soiconsortium.org/corners/fully-depleted-soi/february-2012/5%20-%20Terence%20Hook%20-%20FINFET%20on%20SOI.pdf

http://semimd.com/blog/2011/02/10/partners-test-utb-soi-for-mobile-systems/

http://semimd.com/hars/2011/11/29/fd-soi-bests-finfets-for-mobile-multimedia-socs-st-says-yes/

http://semimd.com/blog/2011/02/14/chenming-hu-welcomes-finfet-vs-utb-soi-race/

http://semimd.com/wp-content/uploads/2011/02/SOIconsortium_FDSOI_QA.pdf

http://semimd.com/wp-content/uploads/2011/02/SOIconsortium_FDSOI_design.pdf

http://semimd.com/blog/2011/12/03/ibm-sees-performance-from-fd-soi-transistors/

http://www.eetimes.com/electronics-news/4231219/FDSOI-risk-FinFETs-SOI-body

http://theasicguy.com/tag/finfet/

From what i can understand from disparate sources, "planar" bulk is DEAD after the 20nm processes... but the twist is that FinFET on SOI is easier to fab, provides better results and can even cost less, attending it can have quite a bunch less steps(below)

>>And if (always the *if*) Intel had gone for a SOI process back them, instead of
>>exploding pipeline lengths and double pumping ALUs... >perhaps the core2 might never had happened...
>
>If we had green eggs, we could have green eggs and ham, if we had some ham.
>
>Intel doesn't do SOI and has very little interest except for silicon photonics.
>
>DK

Someone "close tight" to the foundry industry, not chip marketing, is selling green eggs.. or is other way around ?

http://www.electroiq.com/articles/sst/print/volume-52/issue-11/features/Cover_Article/Comparing_SOI_and_bulk_FinFETs__Performance__manufacturing_variability__and_cost.html

Really it begs the question, because if that analyses is correct, and this news also http://www.eetimes.com/electronics-news/4371063/Silicon-on-insulator-at-ST-and-IBM-closing-gap-with-Intel

" Intel has gone to great lengths to design FD undoped channels for its tri-gate FinFET transistor using standard bulk silicon wafers, which as a result *requires sidewall implant doping(SiO2)* to isolate the channel and prevent excess leakage current into the substrate. "

The process of Intel is transforming a bulk substrate into a SOI(SiO2) one under critical regions(not the all chip i think) of those FinFETs...

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SOI, FD vs. PD	hcl64	04/30/12 08:08 AM
SOI, FD vs. PD	David Kanter	04/30/12 09:59 AM
SOI, FD vs. PD	hcl64	04/30/12 06:10 PM
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SOI, FD vs. PD	hcl64	05/01/12 06:37 AM
SOI, FD vs. PD	David Kanter	05/01/12 08:19 AM
SOI, FD vs. PD	hcl64	05/01/12 07:39 AM
PD-SOI	David Kanter	05/02/12 12:22 PM
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SOI, FD vs. PD	David Kanter	04/30/12 10:16 PM
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Previous discussion of clustered MT	hcl64	04/28/12 09:38 PM
Previous discussion of clustered MT	David Kanter	04/30/12 04:37 PM
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Latency issues	David Kanter	05/02/12 12:01 PM
So, what do people think of these numbers>	Megol	04/21/12 01:57 AM

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Body:	No Text hcl64 (mario.smarq.delete@this.gmail.com) on April 28, 2012 11:44 pm wrote: > David Kanter (dkanter@realworldtech.com) on 4/28/12 wrote: > --------------------------- > >hcl64 (mario.smarq@gmail.com) on 4/28/12 wrote: > >--------------------------- > >>David Kanter (dkanter@realworldtech.com) on 4/28/12 wrote: > >>--------------------------- > >>Yet the total pipeline length of BD is 15 stages without > >the latency hiding effect, so hardly resembling P4. > > > >Do you have any references for that? AMD has never publicly stated the depth, and > >I suspect it's much more like 20 stages. > > > > <a href="http://www.hardocp.com/article/2011/11/29/hardocp_readers_ask_amd_bulldozer_questions/1" target="_blank">http://www.hardocp.com/article/2011/11/29/hardocp_readers_ask_amd_bulldozer_questions/1</a> > > " Mike Butler, Senior Fellow Design Engineer, AMD - The latest architectural advancements > from both AMD and our competitors have incorporated advancements from deeper pipelines. The > pipeline within our latest "Bulldozer" microarchitecture is approximately 25 percent deeper > than that of the previous generation architectures. That deeper pipeline is a key technology > advancement, providing record breaking frequencies and performance improvements " > > GH 12 stages : 121.25=15 > > >>What resembles P4 the most, and most strikingly the Prescott variant, that everybody > >>bashes as being not good and a power hog is IBM z196. > > > >What are you talking about? > > > >>It has proximately the same > >>number of stages(more than 30), is a CISC ISA (perhaps more complex than x86), has > >>complex operand forwarding networks (which can hurt clock >cycle badly) with a > >form of eager execution with >checkpointing > > > >>Its a monster chip with >500mm2 with extensive RAS features(also can hurt clock > >>cycle)... a power hog alright, yet its marketed at 5.2Ghz stock speed, on a 45nm > >>no HKMG SOI process ... i just wonder at IBM* 22nm FinFET >(HKMG) SOI process!. > > > >It's amazing what you can do with a liquid cooled chip that dissipates 250W. > > > > :) just wonder if any chip >500mm2 at 45nm "bulk" no HKMG, > could even reach any close to that on dry ice... > > >>Without wanting to hurt feelings, yes it seems that Intel has the best "bulk" process > >>around bare none today, but perhaps the "marketing gimmicky" of the SOITEC group > >>about SOI offering up to 40% better mobility for high >clock > high performance chips, is not too much out of place. > > > >LOL. It's off by about a factor of 5X. SOI gives at best a 7% performance advantage > >in 65nm and below. The benefits have consistently diminished over time. > > > > Marketing gimmicky perhaps !?, perhaps someone should correct > those guys, because something fishingly hot is going on > > <a href="http://www.soiconsortium.org/corners/fully-depleted-soi/february-2012/index.php" target="_blank">http://www.soiconsortium.org/corners/fully-depleted-soi/february-2012/index.php</a> > > Specially Terence Hook (IBM) > <a href="http://www.soiconsortium.org/corners/fully-depleted-soi/february-2012/5%20-%20Terence%20Hook%20-%20FINFET%20on%20SOI.pdf" target="_blank">http://www.soiconsortium.org/corners/fully-depleted-soi/february-2012/5%20-%20Terence%20Hook%20-%20FINFET%20on%20SOI.pdf</a> > > <a href="http://semimd.com/blog/2011/02/10/partners-test-utb-soi-for-mobile-systems/" target="_blank">http://semimd.com/blog/2011/02/10/partners-test-utb-soi-for-mobile-systems/</a> > > <a href="http://semimd.com/hars/2011/11/29/fd-soi-bests-finfets-for-mobile-multimedia-socs-st-says-yes/" target="_blank">http://semimd.com/hars/2011/11/29/fd-soi-bests-finfets-for-mobile-multimedia-socs-st-says-yes/</a> > > <a href="http://semimd.com/blog/2011/02/14/chenming-hu-welcomes-finfet-vs-utb-soi-race/" target="_blank">http://semimd.com/blog/2011/02/14/chenming-hu-welcomes-finfet-vs-utb-soi-race/</a> > > <a href="http://semimd.com/wp-content/uploads/2011/02/SOIconsortium_FDSOI_QA.pdf" target="_blank">http://semimd.com/wp-content/uploads/2011/02/SOIconsortium_FDSOI_QA.pdf</a> > > <a href="http://semimd.com/wp-content/uploads/2011/02/SOIconsortium_FDSOI_design.pdf" target="_blank">http://semimd.com/wp-content/uploads/2011/02/SOIconsortium_FDSOI_design.pdf</a> > > <a href="http://semimd.com/blog/2011/12/03/ibm-sees-performance-from-fd-soi-transistors/" target="_blank">http://semimd.com/blog/2011/12/03/ibm-sees-performance-from-fd-soi-transistors/</a> > > <a href="http://www.eetimes.com/electronics-news/4231219/FDSOI-risk-FinFETs-SOI-body" target="_blank">http://www.eetimes.com/electronics-news/4231219/FDSOI-risk-FinFETs-SOI-body</a> > > <a href="http://theasicguy.com/tag/finfet/" target="_blank">http://theasicguy.com/tag/finfet/</a> > > From what i can understand from disparate sources, "planar" bulk is DEAD after the 20nm > processes... but the twist is that FinFET on SOI is easier to fab, provides better results > and can even cost less, attending it can have quite a bunch less steps(below) > > >>And if (always the if) Intel had gone for a SOI process back them, instead of > >>exploding pipeline lengths and double pumping ALUs... >perhaps the core2 might never had happened... > > > >If we had green eggs, we could have green eggs and ham, if we had some ham. > > > >Intel doesn't do SOI and has very little interest except for silicon photonics. > > > >DK > > Someone "close tight" to the foundry industry, not chip marketing, > is selling green eggs.. or is other way around ? > > <a href="http://www.electroiq.com/articles/sst/print/volume-52/issue-11/features/Cover_Article/Comparing_SOI_and_bulk_FinFETs__Performance__manufacturing_variability__and_cost.html" target="_blank">http://www.electroiq.com/articles/sst/print/volume-52/issue-11/features/Cover_Article/Comparing_SOI_and_bulk_FinFETs__Performance__manufacturing_variability__and_cost.html</a> > > Really it begs the question, because if that analyses is correct, and this news also <a href="http://www.eetimes.com/electronics-news/4371063/Silicon-on-insulator-at-ST-and-IBM-closing-gap-with-Intel" target="_blank">http://www.eetimes.com/electronics-news/4371063/Silicon-on-insulator-at-ST-and-IBM-closing-gap-with-Intel</a> > > " Intel has gone to great lengths to design FD undoped channels for its tri-gate FinFET transistor > using standard bulk silicon wafers, which as a result requires sidewall implant doping(SiO2) > to isolate the channel and prevent excess leakage current into the substrate. " > > The process of Intel is transforming a bulk substrate into a SOI(SiO2) > one under critical regions(not the all chip i think) of those FinFETs...
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