By: S. Rao (sonny.rao.delete@this.gmail.com), May 14, 2012 2:21 am
Room: Moderated Discussions
I just ran across a reference to this erratum while
researching memory barriers on ARM:
http://infocenter.arm.com/help/topic/com.arm.doc.uan0004a/UAN0004A_a9_read_read.pdf
If I'm reading it correctly, there are two ways of looking
at it. Either stores to the same address can go out of
order, or loads to the same address can go out of order.
Either one of those possibilities violate the ARM
memory consistency model.
The practical implications are similar, although there might
be some differences when there's more than one processor
involved.
The document there references "lock-free" programming, but
doesn't really state that usage of atomics mitigates the
issue. The recommended workaround is to put a memory
barrier between any two loads to the same address (!)
Does anyone else have any information about this?
It seems like a really nasty erratum, and I'm very surprised
that it hasn't gotten much/any press considering how
widely deployed Cortex A9 is these days.
Maybe atomic ops hide the problem sufficiently that it's
not noticed in reality - or people haven't tried really
hammering Cortex A9 cpus with lockless algorithms.
researching memory barriers on ARM:
http://infocenter.arm.com/help/topic/com.arm.doc.uan0004a/UAN0004A_a9_read_read.pdf
If I'm reading it correctly, there are two ways of looking
at it. Either stores to the same address can go out of
order, or loads to the same address can go out of order.
Either one of those possibilities violate the ARM
memory consistency model.
The practical implications are similar, although there might
be some differences when there's more than one processor
involved.
The document there references "lock-free" programming, but
doesn't really state that usage of atomics mitigates the
issue. The recommended workaround is to put a memory
barrier between any two loads to the same address (!)
Does anyone else have any information about this?
It seems like a really nasty erratum, and I'm very surprised
that it hasn't gotten much/any press considering how
widely deployed Cortex A9 is these days.
Maybe atomic ops hide the problem sufficiently that it's
not noticed in reality - or people haven't tried really
hammering Cortex A9 cpus with lockless algorithms.
| Topic | Posted By | Date |
|---|---|---|
| Cortex A9 Erratum 761319 | S. Rao | 05/14/12 02:21 AM |
| Cortex A9 Erratum 761319 | S. Rao | 05/14/12 02:26 AM |
| Cortex A9 Erratum 761319 | nksingh | 05/15/12 06:14 PM |
| Cortex A9 Erratum 761319 | S. Rao | 05/15/12 06:24 PM |
| Cortex A9 Erratum 761319 | none | 05/14/12 04:09 AM |
| Cortex A9 Erratum 761319 | S. Rao | 05/14/12 04:20 AM |
| Cortex A9 Erratum 761319 | Linus Torvalds | 05/14/12 08:14 AM |
| Cortex A9 Erratum 761319 | bakaneko | 05/14/12 09:27 PM |
