By: EduardoS (no.delete@this.spam.com), July 25, 2012 8:12 pm
Room: Moderated Discussions
Unununium (none.delete@this.none.com) on July 25, 2012 5:55 pm wrote:
> This chart was a bad idea when RWT published it years ago, and it's still a bad
> idea today. It's simplistic to the point of being wrong. Peak flops/mm and
> Peak flops/W don't matter. Otherwise, we would have seen widespread Silverthorne
> adoption in HPC after RWT crowned it king last time - which never
> happened.
I agree the chart is a bad idea but for different reasons:
1) It is wrong, take Interlagos for example, a 140W dual chip processor, it have 8 modules, each able to perform 2 FMACs per clock, so 32 flops per clock, right? At 2.6GHz it is a little less than 0.6 DP Flops/Watt, well, turbo may help a little but no way to the ~1.4 DP Flops/Watt in the chart, the DP Flops/mm² looks proportionally wrong as well.
2) I have plotted a chart of 32nm Opterons with the best at each TDP, the chart plotted by Kanter doesn't express very well the relation between power and die size: http://tinypic.com/r/280uuk4/6
> This chart was a bad idea when RWT published it years ago, and it's still a bad
> idea today. It's simplistic to the point of being wrong. Peak flops/mm and
> Peak flops/W don't matter. Otherwise, we would have seen widespread Silverthorne
> adoption in HPC after RWT crowned it king last time - which never
> happened.
I agree the chart is a bad idea but for different reasons:
1) It is wrong, take Interlagos for example, a 140W dual chip processor, it have 8 modules, each able to perform 2 FMACs per clock, so 32 flops per clock, right? At 2.6GHz it is a little less than 0.6 DP Flops/Watt, well, turbo may help a little but no way to the ~1.4 DP Flops/Watt in the chart, the DP Flops/mm² looks proportionally wrong as well.
2) I have plotted a chart of 32nm Opterons with the best at each TDP, the chart plotted by Kanter doesn't express very well the relation between power and die size: http://tinypic.com/r/280uuk4/6
