By: Moritz (better.delete@this.not.tell), July 28, 2012 12:52 pm
Room: Moderated Discussions
EduardoS (no.delete@this.spam.com) on July 27, 2012 5:24 pm wrote:
> other chips have a few MB SRAM which should take about as much space,
> BG/Q looks really a case of reducing power by sacrificing area.
He is right in that a GPU has much less cache, both in area and capacity.
Obviously this eDRAM does not use much power.
But more memory width costs area (drivers) and power too.
Not just the clock-rate decides where you are on the line, but also energy efficient caching. One can replace many low clocked FPUs with fewer higher clocked units and still come out on the high flops/Watt side of the chart using low power cache.
His critique is irrelevant though, because I never ment it the way he read it.
Where you want to be on that line (that is not one) and how much you can move on it, depends on the computational problem you want to use the architecture for.
I assume that the cost per area is unimportant for HPC chips, (low number compared to consumer devices) that explains why they still use CPUs with large power efficient caches in HPC.
> other chips have a few MB SRAM which should take about as much space,
> BG/Q looks really a case of reducing power by sacrificing area.
He is right in that a GPU has much less cache, both in area and capacity.
Obviously this eDRAM does not use much power.
But more memory width costs area (drivers) and power too.
Not just the clock-rate decides where you are on the line, but also energy efficient caching. One can replace many low clocked FPUs with fewer higher clocked units and still come out on the high flops/Watt side of the chart using low power cache.
His critique is irrelevant though, because I never ment it the way he read it.
Where you want to be on that line (that is not one) and how much you can move on it, depends on the computational problem you want to use the architecture for.
I assume that the cost per area is unimportant for HPC chips, (low number compared to consumer devices) that explains why they still use CPUs with large power efficient caches in HPC.
