AMD's ASF even more limited

Article: Haswell Transactional Memory Alternatives
By: Linus Torvalds (, August 22, 2012 10:41 am
Room: Moderated Discussions
Paul A. Clayton ( on August 22, 2012 10:20 am wrote:
> Many critical sections are small--intentionally so because a long
> critical section is likely to reduce parallelism. Without additional (complex)
> hardware to order transactions so that they do not conflict, most large
> transactions might be likely to fail.

Many critical sections are really small, because they may be implementing things like atomic hash chain updates etc. So the lock may be protecting literally just a small handful of instructions - yet the sequence is not just about one or two words, so ll/sc wouldn't work.

That's where people who try to do scaling at any cost will have per-hashchain locks etc, but that eats memory and can cause other complexity problems (locking when moving things between hashchains atomically etc). So many normal programmers will rely on some generic hash library that probably has just a single lock for all the accesses.

That's a wonderful use-case for hardware lock elision. Keep the lock cacheline shared across CPU's, no need for the complexities of multiple locks, things "just work". And I think it's a fairly common case.

More importantly, even if ll/sc could work in some particular case, realistically people wouldn't actually use ll/sc, because it's basically impossible to do portably, and it's not generally amenable to the compiler doing it automatically. In contrast, lock elision with small transactions is amenable to doing automatically from portable source code.

Note: "portable" here doesn't necessarily mean "works across many architectures". It can mean "works together with code that is written to work for a previous generation of the CPU that didn't have the transactional capability". So when I say "portable", I don't mean the Linux kind of "portable to the 30 different architectures we support", I mean the Windows or OSX kind of "we can use the same codebase without major pain for different versions of Intel chips".

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TopicPosted ByDate
Article: Haswell TM AlternativesDavid Kanter08/21/12 10:17 PM
  Article: Haswell TM AlternativesHÃ¥kan Winbom08/22/12 12:52 AM
    Article: Haswell TM AlternativesDavid Kanter08/22/12 02:06 AM
  Article: Haswell TM Alternativesanon08/22/12 09:46 AM
    Article: Haswell TM AlternativesLinus Torvalds08/22/12 10:16 AM
      Article: Haswell TM AlternativesDoug S08/24/12 09:34 AM
    AMD's ASF even more limitedPaul A. Clayton08/22/12 10:20 AM
      AMD's ASF even more limitedLinus Torvalds08/22/12 10:41 AM
        Compiler use of ll/sc?Paul A. Clayton08/28/12 10:28 AM
          Compiler use of ll/sc?Linus Torvalds09/08/12 01:58 PM
            Lock recognition?Paul A. Clayton09/10/12 02:17 PM
              Sorry, I was confusedPaul A. Clayton09/13/12 11:56 AM
  Filter to detect store conflictsPaul A. Clayton08/22/12 10:19 AM
  Article: Haswell TM Alternativesbakaneko08/22/12 03:02 PM
    Article: Haswell TM AlternativesDavid Kanter08/22/12 03:45 PM
      Article: Haswell TM Alternativesbakaneko08/22/12 10:56 PM
  Cache line granularity?Paul A. Clayton08/28/12 10:28 AM
    Cache line granularity?David Kanter08/31/12 09:13 AM
      A looser definition might have advantagesPaul A. Clayton09/01/12 07:29 AM
    Cache line granularity?rwessel08/31/12 08:54 PM
      Alpha load locked granularityPaul A. Clayton09/01/12 07:29 AM
        Alpha load locked granularityanon09/02/12 06:23 PM
          Alpha pages groupsPaul A. Clayton09/03/12 05:16 AM
  An alternative implementationMaynard Handley11/20/12 10:52 PM
    An alternative implementationbakaneko11/21/12 06:52 AM
      Guarding unread values?Paul A. Clayton11/21/12 09:39 AM
        Guarding unread values?bakaneko11/21/12 12:25 PM
    TM granularity and versioningPaul A. Clayton11/21/12 09:27 AM
      TM granularity and versioningMaynard Handley11/21/12 11:52 AM
        Indeed, TM (and coherence) has devilish details (NT)Paul A. Clayton11/21/12 11:56 AM
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