Cache line granularity?

Article: Haswell Transactional Memory Alternatives
By: Paul A. Clayton (, August 28, 2012 10:28 am
Room: Moderated Discussions
I wonder if defining the granularity for RTM to be cache line size is appropriate.

Such would seem to significantly constrain the implementation of finer-grained monitoring. An implementation could monitor at a finer granularity, mainly avoiding some data communication latency, as long as a single order of atomic actions could be guaranteed; but architecturally allowing (but not requiring) finer-grained monitoring might modestly simplify hardware that exploits lack of access-grained conflict.

There does not appear to be much, if any, semantic difference between fine-grained and cache-line granular monitoring since for any collection of transactions that do not conflict at access-level granularity, any ordering of these transactions will be acceptable. (Because hardware could be clever in avoiding transaction failures, it seems that portable software [i.e., working with extremely clever and with simple implementations with the same cache line size] could not even use such to observe the density of "conflicts".)

I wonder if using monitor-line size (introduced for MONITOR/MWAIT)--or something like it--would be better. The monitor-line size includes a minimum and maximum size. Such a range would seem to allow greater freedom of implementation. Alternatively, an architectural minimum size might be defined as the specific access size (which is the minimum required for transactional semantics) and the maximum size might be defined as the cache line size.

Using the cache line size does have the minor annoyance that performance portability becomes more difficult. (The Alpha architectural suggestion for portability of not placing two atomic operands within the same 8 KiB page seems a bit excessive.) Fixing the maximum "monitor-line" size at 64 bytes might not be unreasonable in order to simplify portable software.

By the way, it was interesting to read that Intel (for x86, at least) defines a cache line as being a subset of a cache sector. (I am used to the reverse use of the terms.)
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TopicPosted ByDate
Article: Haswell TM AlternativesDavid Kanter08/21/12 10:17 PM
  Article: Haswell TM AlternativesHåkan Winbom08/22/12 12:52 AM
    Article: Haswell TM AlternativesDavid Kanter08/22/12 02:06 AM
  Article: Haswell TM Alternativesanon08/22/12 09:46 AM
    Article: Haswell TM AlternativesLinus Torvalds08/22/12 10:16 AM
      Article: Haswell TM AlternativesDoug S08/24/12 09:34 AM
    AMD's ASF even more limitedPaul A. Clayton08/22/12 10:20 AM
      AMD's ASF even more limitedLinus Torvalds08/22/12 10:41 AM
        Compiler use of ll/sc?Paul A. Clayton08/28/12 10:28 AM
          Compiler use of ll/sc?Linus Torvalds09/08/12 01:58 PM
            Lock recognition?Paul A. Clayton09/10/12 02:17 PM
              Sorry, I was confusedPaul A. Clayton09/13/12 11:56 AM
  Filter to detect store conflictsPaul A. Clayton08/22/12 10:19 AM
  Article: Haswell TM Alternativesbakaneko08/22/12 03:02 PM
    Article: Haswell TM AlternativesDavid Kanter08/22/12 03:45 PM
      Article: Haswell TM Alternativesbakaneko08/22/12 10:56 PM
  Cache line granularity?Paul A. Clayton08/28/12 10:28 AM
    Cache line granularity?David Kanter08/31/12 09:13 AM
      A looser definition might have advantagesPaul A. Clayton09/01/12 07:29 AM
    Cache line granularity?rwessel08/31/12 08:54 PM
      Alpha load locked granularityPaul A. Clayton09/01/12 07:29 AM
        Alpha load locked granularityanon09/02/12 06:23 PM
          Alpha pages groupsPaul A. Clayton09/03/12 05:16 AM
  An alternative implementationMaynard Handley11/20/12 10:52 PM
    An alternative implementationbakaneko11/21/12 06:52 AM
      Guarding unread values?Paul A. Clayton11/21/12 09:39 AM
        Guarding unread values?bakaneko11/21/12 12:25 PM
    TM granularity and versioningPaul A. Clayton11/21/12 09:27 AM
      TM granularity and versioningMaynard Handley11/21/12 11:52 AM
        Indeed, TM (and coherence) has devilish details (NT)Paul A. Clayton11/21/12 11:56 AM
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