Alpha pages groups

Article: Haswell Transactional Memory Alternatives
By: Paul A. Clayton (paaronclayton.delete@this.gmail.com), September 3, 2012 5:16 am
Room: Moderated Discussions
anon (anon.delete@this.anon.com) on September 2, 2012 6:23 pm wrote:
> Paul A. Clayton (paaronclayton.delete@this.gmail.com) on
> September 1, 2012 7:29 am wrote:
[snip]
>> (Of course, Alpha did eventually support 64 KiB base
>> pages.)
>
> Didn't Alpha always support 64 KB, in addition to 8 KB, 512
> KB, and 2 MB page sizes?

At least some of the Alpha documentation calls such larger translation units page groups (e.g., the 21264 Microprocessor Hardware Reference Manual: "with each entry able to map a single 8KB page or a group of 8, 64, or 512 8KB pages"--that would be 4 MiB not 2 MiB, by the way). (Note I did use "base pages" to avoid confusion.)

Looking at the 21064A data sheet, such seem to have been called large pages, but less variety was supported in the instruction translation buffer ("The first eight page table entries provide small page (8K byte) translations while the remaining four provide large page (4 MB) translations.") (The HRM also indicates that "superpages" were supported for OS use that directly mapped the entire physical address space [multiple times, presumably using modulo addressing--the 21164PC data sheet seems to confirm this].)

(The 21164PC data sheet seems a bit less consistent in terminology: "The buffer stores recently used instruction stream (Istream) address translations and protection information for pages ranging from 8KB to 512KB" but also "Each entry supports all four granularity hint-bit combinations, so that a single DTB entry can provide translation for up to 512 contiguously mapped, 8-KB pages.")
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TopicPosted ByDate
Article: Haswell TM AlternativesDavid Kanter08/21/12 10:17 PM
  Article: Haswell TM AlternativesHÃ¥kan Winbom08/22/12 12:52 AM
    Article: Haswell TM AlternativesDavid Kanter08/22/12 02:06 AM
  Article: Haswell TM Alternativesanon08/22/12 09:46 AM
    Article: Haswell TM AlternativesLinus Torvalds08/22/12 10:16 AM
      Article: Haswell TM AlternativesDoug S08/24/12 09:34 AM
    AMD's ASF even more limitedPaul A. Clayton08/22/12 10:20 AM
      AMD's ASF even more limitedLinus Torvalds08/22/12 10:41 AM
        Compiler use of ll/sc?Paul A. Clayton08/28/12 10:28 AM
          Compiler use of ll/sc?Linus Torvalds09/08/12 01:58 PM
            Lock recognition?Paul A. Clayton09/10/12 02:17 PM
              Sorry, I was confusedPaul A. Clayton09/13/12 11:56 AM
  Filter to detect store conflictsPaul A. Clayton08/22/12 10:19 AM
  Article: Haswell TM Alternativesbakaneko08/22/12 03:02 PM
    Article: Haswell TM AlternativesDavid Kanter08/22/12 03:45 PM
      Article: Haswell TM Alternativesbakaneko08/22/12 10:56 PM
  Cache line granularity?Paul A. Clayton08/28/12 10:28 AM
    Cache line granularity?David Kanter08/31/12 09:13 AM
      A looser definition might have advantagesPaul A. Clayton09/01/12 07:29 AM
    Cache line granularity?rwessel08/31/12 08:54 PM
      Alpha load locked granularityPaul A. Clayton09/01/12 07:29 AM
        Alpha load locked granularityanon09/02/12 06:23 PM
          Alpha pages groupsPaul A. Clayton09/03/12 05:16 AM
  An alternative implementationMaynard Handley11/20/12 10:52 PM
    An alternative implementationbakaneko11/21/12 06:52 AM
      Guarding unread values?Paul A. Clayton11/21/12 09:39 AM
        Guarding unread values?bakaneko11/21/12 12:25 PM
    TM granularity and versioningPaul A. Clayton11/21/12 09:27 AM
      TM granularity and versioningMaynard Handley11/21/12 11:52 AM
        Indeed, TM (and coherence) has devilish details (NT)Paul A. Clayton11/21/12 11:56 AM
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