By: David Kanter (dkanter.delete@this.realworldtech.com), September 20, 2012 12:24 pm
Room: Moderated Discussions
Eric (eric.kjellen.delete@this.gmail.com) on September 20, 2012 10:44 am wrote:
> David Kanter (dkanter.delete@this.realworldtech.com) on September 18, 2012 5:20
> pm wrote:
> > Generally you use
> > capacitors to stabilize Vcc, and you
> want as few as possible, because they eat
> > up a ton of area. I don't
> think this is a realistic idea.
> >
>
> Is this the reason, or part of the
> reason, that POWER7 has such low transistor density (1.2B transistors in 567
> mm^2 on a 45nm process)?
Sort of. If you look at IBM's eDRAM, it's about 3X the density of SRAM. Each cell uses 1T1D vs. 6T for SRAM. So doing the math, you have 3T3D per unit area vs. 6T.
That's just for the L3 data arrays. The L3 tags are still SRAM, and the cores+L1+L2 are normal. How those components compare is quite unclear. Given the high frequencies, it's quite possible that the cores aren't as dense as other designs.
David
> David Kanter (dkanter.delete@this.realworldtech.com) on September 18, 2012 5:20
> pm wrote:
> > Generally you use
> > capacitors to stabilize Vcc, and you
> want as few as possible, because they eat
> > up a ton of area. I don't
> think this is a realistic idea.
> >
>
> Is this the reason, or part of the
> reason, that POWER7 has such low transistor density (1.2B transistors in 567
> mm^2 on a 45nm process)?
Sort of. If you look at IBM's eDRAM, it's about 3X the density of SRAM. Each cell uses 1T1D vs. 6T for SRAM. So doing the math, you have 3T3D per unit area vs. 6T.
That's just for the L3 data arrays. The L3 tags are still SRAM, and the cores+L1+L2 are normal. How those components compare is quite unclear. Given the high frequencies, it's quite possible that the cores aren't as dense as other designs.
David
