By: David Kanter (dkanter.delete@this.realworldtech.com), October 11, 2012 3:00 pm
Room: Moderated Discussions
slacker (s.delete@this.lack.er) on October 11, 2012 1:35 pm wrote:
> Kevin G (kevin.delete@this.cubitdesigns.com) on October 9, 2012 3:04 pm
> wrote:
> >
> > I've found reference to
> > 291 Mbit parts from Intel on
> their 32 nm process. No indication of die size for
> > a real density
> comparison.
>
> That's their SRAM test vehicle. They do it for every
> process:
>
> 32nm - 291Mb
> 45nm - 153Mb
> 65nm - 70Mb
> 90nm - 50Mb
> 130nm -
> ???
> 180nm - 18Mb
>
> > My main point though is even with a 1/6th
> >
> reduction in density it would still be good enough. For example, a system
>
> > supporting 192 GB max going to 32 GB max with better bandwidth and
> latency would
> > be a good trade off for some applications.
>
> The last
> hold-out for SRAMs in the HPC business were Vector supercomputers, and even they
> quit using SRAMs long ago. It's just too expensive, and DRAM offers you so much
> more capacity.
Also, SRAM leakage is dramatically higher than DRAM leakage. In the context of large HPC systems, memory power is quite significant and a growing problem. Moving to SRAM would only make things worse.
Admittedly, I'm not sure how memory power breaks down between static and dynamic sources. It's possible that SRAM would have better dynamic power, offsetting the leakage problems...but it's equally possible that it would make things worse overall.
Together with the density issues, SRAM just doesn't seem like a viable option. Potentially, you could add some sort of packaged DRAM/SRAM for higher bandwidth and that just seems like a much more attractive option.
David
> Kevin G (kevin.delete@this.cubitdesigns.com) on October 9, 2012 3:04 pm
> wrote:
> >
> > I've found reference to
> > 291 Mbit parts from Intel on
> their 32 nm process. No indication of die size for
> > a real density
> comparison.
>
> That's their SRAM test vehicle. They do it for every
> process:
>
> 32nm - 291Mb
> 45nm - 153Mb
> 65nm - 70Mb
> 90nm - 50Mb
> 130nm -
> ???
> 180nm - 18Mb
>
> > My main point though is even with a 1/6th
> >
> reduction in density it would still be good enough. For example, a system
>
> > supporting 192 GB max going to 32 GB max with better bandwidth and
> latency would
> > be a good trade off for some applications.
>
> The last
> hold-out for SRAMs in the HPC business were Vector supercomputers, and even they
> quit using SRAMs long ago. It's just too expensive, and DRAM offers you so much
> more capacity.
Also, SRAM leakage is dramatically higher than DRAM leakage. In the context of large HPC systems, memory power is quite significant and a growing problem. Moving to SRAM would only make things worse.
Admittedly, I'm not sure how memory power breaks down between static and dynamic sources. It's possible that SRAM would have better dynamic power, offsetting the leakage problems...but it's equally possible that it would make things worse overall.
Together with the density issues, SRAM just doesn't seem like a viable option. Potentially, you could add some sort of packaged DRAM/SRAM for higher bandwidth and that just seems like a much more attractive option.
David
