By: David Kanter (dkanter.delete@this.realworldtech.com), November 14, 2012 11:09 am
Room: Moderated Discussions
Joe (you.delete@this.atyourperil.com) on November 14, 2012 10:38 am wrote:
> randomshinichi (randomshinichi4869.delete@this.gmail.com) on November 14, 2012 2:53 am wrote:
> > Since when did L3 cache suddenly become LLC? Or is this some kind of Intel architecture
> > specific term? I think I've been seeing LLC floating around since Sandy Bridge.
>
> It can be a handy convention when different architectures, with different cache hierarchies, end
> up using their "outermost" level of cache for some of the same things (eg coherency), allowing
> you to draw comparisons without getting bogged down in the details. It's not surprising this site,
> which spends more time comparing different architectures than most, would be fond of it.
Actually, I hated the term initially, but it's grown on me. I'd much prefer to describe caches in terms of levels in the hierarchy...but that's increasingly difficult.
As a simple example, is Intel's uop cache a L0 instruction cache? Where does it fit.
More telling is that the LLC in Sandy Bridge and Haswell is used by both the CPU and GPU. In the context of the CPU, it is the L3. However, there are actually 4 levels of cache for certain types of GPU data, with the LLC being the last level. So how do you reconcile those issues? The term LLC does a good job.
DK
> randomshinichi (randomshinichi4869.delete@this.gmail.com) on November 14, 2012 2:53 am wrote:
> > Since when did L3 cache suddenly become LLC? Or is this some kind of Intel architecture
> > specific term? I think I've been seeing LLC floating around since Sandy Bridge.
>
> It can be a handy convention when different architectures, with different cache hierarchies, end
> up using their "outermost" level of cache for some of the same things (eg coherency), allowing
> you to draw comparisons without getting bogged down in the details. It's not surprising this site,
> which spends more time comparing different architectures than most, would be fond of it.
Actually, I hated the term initially, but it's grown on me. I'd much prefer to describe caches in terms of levels in the hierarchy...but that's increasingly difficult.
As a simple example, is Intel's uop cache a L0 instruction cache? Where does it fit.
More telling is that the LLC in Sandy Bridge and Haswell is used by both the CPU and GPU. In the context of the CPU, it is the L3. However, there are actually 4 levels of cache for certain types of GPU data, with the LLC being the last level. So how do you reconcile those issues? The term LLC does a good job.
DK
