By: EduardoS (no.delete@this.spam.com), November 15, 2012 6:21 am
Room: Moderated Discussions
anon (anon.delete@this.anon.com) on November 15, 2012 6:14 am wrote:
> Any port? Including Load/Store AGU?
"In theory", a possible way of executing them, I didn't had the manual at hand.
> And Intel manual says: Some micro-ops can execute to completion during rename and are removed
> from the pipeline at that point, effectively costing no execution bandwidth. These include:
> • Zero idioms (dependency breaking idioms)
> • NOP
> • VZEROUPPER
> • FXCHG
From Intel manual? Nice, no need to speculate.
Now I just wonder way mov elimination wasn't implemented earlier.
> Any port? Including Load/Store AGU?
"In theory", a possible way of executing them, I didn't had the manual at hand.
> And Intel manual says: Some micro-ops can execute to completion during rename and are removed
> from the pipeline at that point, effectively costing no execution bandwidth. These include:
> • Zero idioms (dependency breaking idioms)
> • NOP
> • VZEROUPPER
> • FXCHG
From Intel manual? Nice, no need to speculate.
Now I just wonder way mov elimination wasn't implemented earlier.



