By: anon (anon.delete@this.anon.com), November 15, 2012 6:31 am
Room: Moderated Discussions
EduardoS (no.delete@this.spam.com) on November 15, 2012 6:21 am wrote:
> anon (anon.delete@this.anon.com) on November 15, 2012 6:14 am wrote:
> > Any port? Including Load/Store AGU?
>
> "In theory", a possible way of executing them, I didn't had the manual at hand.
>
> > And Intel manual says: Some micro-ops can execute to completion during rename and are removed
> > from the pipeline at that point, effectively costing no execution bandwidth. These include:
> > • Zero idioms (dependency breaking idioms)
> > • NOP
> > • VZEROUPPER
> > • FXCHG
>
> From Intel manual? Nice, no need to speculate.
Yes, cite from "Intel 64 and IA-32 Architectures Optimization Reference Manual", section 2.1.3.1.
> Now I just wonder way mov elimination wasn't implemented earlier.
Maybe because PRF-based design is not used until Sandy (except NetBurst)?
> anon (anon.delete@this.anon.com) on November 15, 2012 6:14 am wrote:
> > Any port? Including Load/Store AGU?
>
> "In theory", a possible way of executing them, I didn't had the manual at hand.
>
> > And Intel manual says: Some micro-ops can execute to completion during rename and are removed
> > from the pipeline at that point, effectively costing no execution bandwidth. These include:
> > • Zero idioms (dependency breaking idioms)
> > • NOP
> > • VZEROUPPER
> > • FXCHG
>
> From Intel manual? Nice, no need to speculate.
Yes, cite from "Intel 64 and IA-32 Architectures Optimization Reference Manual", section 2.1.3.1.
> Now I just wonder way mov elimination wasn't implemented earlier.
Maybe because PRF-based design is not used until Sandy (except NetBurst)?
