Lack of paging structure cache information

Article: Silvermont, Intel's Low Power Architecture
By: Paul A. Clayton (paaronclayton.delete@this.gmail.com), May 7, 2013 5:51 am
Room: Moderated Discussions
anon (anon.delete@this.anon.com) on May 6, 2013 9:35 pm wrote:
> Paul A. Clayton (paaronclayton.delete@this.gmail.com) on May 6, 2013 9:27 pm wrote:
[snip]
>> There is, of course, the highly unlikely possibility that the huge page TLB entries are also used to cache
>> PDEs (as I have often suggested). If that was the case, the number of entries might be even larger and
>> still be reasonably useful. Since neither Intel nor AMD have ever done this (but instead used separate
>> caching structures for PDEs et al.), I am extremely skeptical that such flexibility is supported.
>
> What kind of caching structures do they use? Do you have any data about this?

I do not know if any size information has been made public (and discovering such information with test programs would be difficult--e.g., needing to prevent ordinary cache hits for page table cache blocks--and the interest in such information is probably very limited, so I doubt it is publicly available). The basic structural information for Intel's mechanism is included in Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 3A: System Programming Guide, Part 1
, sections 4.10.3 and 4.10.4.

Intel's mechanism seems to have separate structures for caching PDE (PML2), PDPTE (PML3), and PML4. Like a TLB, each entry contains the permission information (which is simply the value from the in-memory entry for the highest level [PML4] but for lower level entries some fields must be ANDed [for Read/Write, User/Supervisor flags] or ORed [for eXecute Deny flags] with the values of the higher level entries) as well as a pointer to the page associated with that part of the page table. Like TLBs, these structures are not snooped for changes in the backing store (i.e., main memory) but must be explicitly invalidated.

When there is a TLB miss, the hardware page table walker can look at the PDE (PML2) cache for the 2MiB section of the virtual memory address. On a hit, only a single memory access (which might be a hit in the ordinary cache) is needed to fill the TLB. On a miss, the PDPTE (PML3) cache would be checked. On a hit, one memory access would find the appropriate PDE (PML2), presumably loading its information into the PDE cache, and use the information from the PDE to satisfy the TLB miss. (Obviously, such structures could be probed in parallel to reduce latency. [Exploiting a desire for such parallel access, one might use dictionary-based compression. E.g., a PDE cache entry might replace the MSbits of its tag with a pointer into the PDPTE cache. With 128 PDPTE cache entries, this could save more than 20 tag bits [PCID bits + 48 supported virtual address bits - 21 address bits exclusive to the PDE - 7 bits of the PDPTE cache entry number] per PDE cache entry; but such would require inclusion and increase management complexity.])

Thomas W. Barr et al.'s "Translation Caching: Skip, Don’t Walk (the Page Table)" provides an overview of AMD's mechanism (which may have changed), as well as Intel's. AMD's mechanism just provided a separate data cache for paging structure information. I.e., the information is accessed by physical memory addresses and the page table must be fully walked as normal. (Effectively this "only" avoids conflicts with use in the ordinary cache and allows the hardware page table walker to have fast [and non-conflicting] access to such storage.)
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                      quad-core since Nov 2006mpx05/13/13 12:34 AM
                        quad-core since Nov 2006RichardC05/13/13 02:48 AM
                          quad-core since Nov 2006Jukka Larja05/14/13 10:34 AM
                            quad-core since Nov 2006RichardC05/14/13 11:23 AM
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                                  Thanks. Mark Roulo05/14/13 05:05 PM
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                        SMT is a dodo birdPatrick Chase05/17/13 08:43 AM
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                          SMT is a dodo birdRichardC05/15/13 07:53 AM
                            SMT is a dodo birdRicardo B05/15/13 08:31 AM
                              SMT is a dodo birdRichardC05/15/13 10:13 AM
                                SMT is a dodo birdRicardo B05/15/13 11:43 AM
                                  SMT is a dodo birdRichardC05/15/13 12:15 PM
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              SMT is a dodo birdmpx05/12/13 05:13 PM
                Thanks for the actual research effort! (NT)Paul A. Clayton05/13/13 04:43 AM
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                        How Does Silvermont Compare To A15?Exophase05/17/13 09:33 PM
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                              FYI Tegra4 has A15 in it also, so 3 devicesS. Rao05/22/13 09:06 AM
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                                              Quibbling on multithreadingrwessel06/02/13 10:54 PM
                                                Exploiting for SMT was my "contribution"Paul A. Clayton06/03/13 03:53 AM
                                            Silvermont architecture in-depth articleMichael S06/01/13 09:49 AM
                        Silvermont architecture in-depth articleRicardo B05/30/13 03:41 PM
                          Didn't notice how this was to be organized...Sebastian Soeiro05/30/13 06:55 PM
          Silvermont, not Saltwell? (NT)papapapa05/28/13 03:33 PM
            Of course. Not enough sleep. (NT)Ricardo B05/29/13 01:27 PM
  No out-of-order in FP cluster of silvermont?anon06/28/13 02:27 AM
    No out-of-order in FP cluster of silvermont?Michael S06/28/13 03:52 AM
      No out-of-order in FP cluster of silvermont?Exophase06/28/13 12:54 PM
        No out-of-order in FP cluster of silvermont?Michael S06/29/13 10:21 AM
          No out-of-order in FP cluster of silvermont?Exophase06/29/13 08:07 PM
      No out-of-order in FP cluster of silvermont?Linus Torvalds06/29/13 11:22 AM
        No out-of-order in FP cluster of silvermont?anon06/29/13 04:26 PM
          No out-of-order in FP cluster of silvermont?EduardoS06/29/13 05:50 PM
            No out-of-order in FP cluster of silvermont?anon06/29/13 08:15 PM
              No out-of-order in FP cluster of silvermont?EduardoS06/29/13 08:31 PM
                No out-of-order in FP cluster of silvermont?anon06/30/13 01:53 AM
                  No out-of-order in FP cluster of silvermont?EduardoS06/30/13 04:24 AM
                    No out-of-order in FP cluster of silvermont?anon06/30/13 09:41 AM
                      No out-of-order in FP cluster of silvermont?EduardoS06/30/13 12:26 PM
                        No out-of-order in FP cluster of silvermont?anon06/30/13 11:32 PM
                          No out-of-order in FP cluster of silvermont?EduardoS07/01/13 04:40 PM
                            No out-of-order in FP cluster of silvermont?anon07/01/13 05:44 PM
                            No out-of-order in FP cluster of silvermont?Michael S07/02/13 04:40 AM
                              No out-of-order in FP cluster of silvermont?Exophase07/02/13 08:03 AM
                              No out-of-order in FP cluster of silvermont?EduardoS07/02/13 04:20 PM
                          No out-of-order in FP cluster of silvermont?Patrick Chase07/02/13 08:25 AM
                      No out-of-order in FP cluster of silvermont?Etienne07/02/13 03:36 AM
                        No out-of-order in FP cluster of silvermont?anon07/02/13 06:13 AM
                          No out-of-order in FP cluster of silvermont?Patrick Chase07/02/13 09:03 AM
                            No out-of-order in FP cluster of silvermont?anon07/02/13 03:12 PM
                              No out-of-order in FP cluster of silvermont?Patrick Chase07/02/13 03:43 PM
                                No out-of-order in FP cluster of silvermont?anon07/02/13 04:47 PM
                                  No out-of-order in FP cluster of silvermont?Patrick Chase07/02/13 06:36 PM
                                    No out-of-order in FP cluster of silvermont?anon07/02/13 08:03 PM
                                      No out-of-order in FP cluster of silvermont?Symmetry07/03/13 06:14 AM
                                        No out-of-order in FP cluster of silvermont?Patrick Chase07/03/13 08:04 PM
                                          No out-of-order in FP cluster of silvermont?Patrick Chase07/04/13 02:23 AM
                        No out-of-order in FP cluster of silvermont?Patrick Chase07/02/13 09:01 AM
                          No out-of-order in FP cluster of silvermont?Etienne07/03/13 02:26 AM
                            layer 2 cache behaviourEtienne07/05/13 02:14 AM
                              layer 2 cache behaviourMichael S07/05/13 05:41 AM
                                layer 2 cache behaviourEtienne07/05/13 08:15 AM
                              layer 2 cache behaviourPatrick Chase07/05/13 10:37 AM
                                layer 2 cache behaviourMichael S07/06/13 09:57 AM
                                  layer 2 cache behaviourPatrick Chase07/06/13 11:08 AM
                                    layer 2 cache behaviourPatrick Chase07/06/13 11:19 AM
                                    layer 2 cache behaviourEtienne07/08/13 02:10 AM
                                      layer 2 cache behaviourPatrick Chase07/08/13 09:02 AM
                                  layer 2 cache behaviourPatrick Chase07/06/13 01:15 PM
                                  layer 2 cache behaviourUngo07/09/13 02:24 PM
                      No out-of-order in FP cluster of silvermont?Patrick Chase07/02/13 07:43 AM
                  No out-of-order in FP cluster of silvermont?Patrick Chase07/02/13 07:34 AM
                    No out-of-order in FP cluster of silvermont?anon07/02/13 03:15 PM
            No out-of-order in FP cluster of silvermont?none06/30/13 04:03 AM
              No out-of-order in FP cluster of silvermont?EduardoS06/30/13 04:45 AM
                No out-of-order in FP cluster of silvermont?none06/30/13 05:28 AM
                  No out-of-order in FP cluster of silvermont?EduardoS06/30/13 12:27 PM
        No out-of-order in FP cluster of silvermont?x06/30/13 02:54 AM
          No out-of-order in FP cluster of silvermont?Foo_06/30/13 05:15 AM
        No out-of-order in FP cluster of silvermont?rwessel06/30/13 09:11 PM
          No out-of-order in FP cluster of silvermont?Linus Torvalds07/01/13 12:40 PM
            No out-of-order in FP cluster of silvermont?Patrick Chase07/02/13 09:35 AM
              No out-of-order in FP cluster of silvermont?Linus Torvalds07/02/13 10:18 AM
            FPU in integer codes07/02/13 10:38 AM
              FPU in integer codesPatrick Chase07/02/13 10:56 AM
              FPU in integer codesLinus Torvalds07/02/13 11:12 AM
                FPU in integer codesPatrick Chase07/02/13 11:34 AM
                  FPU in integer codesLinus Torvalds07/02/13 12:55 PM
        No out-of-order in FP cluster of silvermont?06/30/13 10:42 PM
          No out-of-order in FP cluster of silvermont?bakaneko07/03/13 02:54 AM
        What about integer SIMD?Exophase06/30/13 11:44 PM
          What about integer SIMD?anon07/01/13 12:45 AM
            What about integer SIMD?Michael S07/01/13 07:57 AM
              What about integer SIMD?rwessel07/01/13 02:39 PM
                What about integer SIMD?Michael S07/01/13 03:11 PM
                  What about integer SIMD?EduardoS07/01/13 05:04 PM
                    What about integer SIMD?Michael S07/01/13 11:32 PM
          What about integer SIMD?hi07/01/13 07:15 AM
            What about integer SIMD?Exophase07/01/13 09:50 AM
            What about integer SIMD?David Kanter07/02/13 12:20 PM
              What about integer SIMD?hi07/02/13 02:48 PM
                What about integer SIMD?David Kanter07/04/13 02:19 PM
  Silvermont architecture in-depth articleSebastian Soeiro07/30/13 08:34 AM
    TLBs are caches of page tablesPaul A. Clayton07/30/13 10:03 AM
      TLBs are caches of page tablesSebastian Soeiro07/30/13 12:18 PM
        TLBs are caches of page tablesPaul A. Clayton07/30/13 02:59 PM
          TLBs are caches of page tablesSebastian Soeiro07/30/13 04:27 PM
            TLBs are caches of page tablesrwessel07/30/13 06:01 PM
              TLBs are caches of page tablesSebastian Soeiro07/31/13 01:15 PM
                Floorplan images show physical locationsPaul A. Clayton07/31/13 03:11 PM
                  Floorplan images show physical locationsSebastian Soeiro07/31/13 08:12 PM
                    Floorplan images show physical locationsrwessel07/31/13 11:21 PM
                      Floorplan images show physical locationsSebastian Soeiro08/02/13 11:58 AM
                        Floorplan images show physical locationsAntti-Ville Tuunainen08/02/13 01:09 PM
                        Floorplan images show physical locationsStubabe08/02/13 06:49 PM
                          Floorplan images show physical locationsSebastian Soeiro08/03/13 07:23 AM
                            Floorplan images show physical locationsrwessel08/03/13 10:16 PM
                            Floorplan images show physical locationsMelody Speer08/04/13 03:11 AM
                              Floorplan images show physical locationsSebastian Soeiro08/04/13 04:42 PM
                                Floorplan images show physical locationsrwessel08/04/13 09:58 PM
                                  Floorplan images show physical locationsSebastian Soeiro08/07/13 02:33 PM
                                    Floorplan images show physical locationsrwessel08/08/13 12:03 PM
                                      Floorplan images show physical locationsSebastian Soeiro08/11/13 08:20 AM
                                        Page tables are set up by the OSPaul A. Clayton08/11/13 12:25 PM
                                          Page tables are set up by the OSSebastian Soeiro08/16/13 07:43 PM
                                            Multilevel page table formatPaul A. Clayton08/17/13 10:18 AM
                                              Multilevel page table formatSebastian Soeiro08/19/13 02:28 PM
                                                Multilevel page table formatrwessel08/19/13 11:08 PM
                                                  Multilevel page table formatSebastian Soeiro08/22/13 03:52 PM
                                                    Multilevel page table formatTREZA08/22/13 04:30 PM
                                                    Multilevel page table formatrwessel08/23/13 09:58 PM
                                                      Multilevel page table formatSebastian Soeiro08/25/13 07:20 AM
                TLBs are caches of page tablesrwessel07/31/13 11:41 PM
                  TLBs are caches of page tablesSebastian Soeiro08/02/13 11:51 AM
                    TLBs are caches of page tablesrwessel08/02/13 05:55 PM
  Silvermont instruction schedulingHugo Décharnes10/02/13 02:25 AM
    Silvermont instruction schedulingMichael S10/02/13 03:29 AM
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