OoO window is limited

By: Paul A. Clayton (paaronclayton.delete@this.gmail.com), December 4, 2014 1:06 pm
Room: Moderated Discussions
anon (anon.delete@this.anon.com) on December 4, 2014 10:15 am wrote:
> Paul A. Clayton (paaronclayton.delete@this.gmail.com) on December 4, 2014 9:11 am wrote:

[snip]

> There is the forward progress section. Although that is for system-wide forward
> progress.

(I did not notice that next section. Thank you for bringing it to my attention.)

Making guarantees about system-wide forward progress is also an optional implementation-specific feature. (A system can also have unadvertised implementation-specific features. Using undocumented behavior as statistical information for performance tuning might be reasonable, but it can be dangerous to assume one understands the implementation so completely that one can take a behavior as guaranteed, even if it seems the only reasonable explanation of observed behavior. (Even if one determined that a given chip is implemented such that the behavior is guaranteed, it is possible that defects even within the same stepping might cause deviation while still upholding architectural behavior and so being sellable.)

> What I remember is that POWER CPUs also guarantee individual forward
> progress given particular restrictions on the critical section.
>
> I can't find the reference yet.

It does not surprise me that a more recent POWER implementation would have stronger guarantees since IBM is a high-end systems vendor (iSeries could broadly exploit such implementation-specific features since it uses an intermediate binary format; for pSeries, AIX and its system libraries (and DB2) could readily exploit such features and modifying selected open source software might be practical).

[snip]

> Power ISA does not it seems, but it allows particular implementations to. POWER CPUs do.
> Software does actually make some assumptions about it too. Linux does not include "backoff"
> and livelock protection in its primitives (like e.g., compxchg based SPARC does).

Interesting.

[snip]

>> (A perhaps better interface would allow each requester to ask for the response to be put in a
>> mailbox since the result is probably not an immediate data dependency. I suppose such could be
>> kludged in to existing systems by adding an undefined state for blocks of memory, so the
>
> What's wrong with existing non blocking loads or OOOE mechanism or avoiding a stall?

OoO has a relatively limited window and using it for this would be like not allowing later instructions to commit because a prefetch instruction has not yet committed. The above mentioned mechanism would be more like (software) asynchronous I/O or stalling the reading thread and spawning a thread to continue with the portion of the task that does not have a data dependency on the read (which thread would join with the stalled reading thread when its non-dependent work was done and might check to see if the value is ready early). Supporting metadata allows software to use the full data range and avoids the need for hardware and software collaboration on how metadata is encoded in the data. (The other thread might be dependent on the validity of the pending read. E.g., a higher level software recovery mechanism might be required if a hardware failure or other event prevents the value from ever being available, but such would be required anyway for the permanently stalled thread.)

I don't know of any ISA that provides, e.g., a fire-and-forget atomic increment (which might be useful for performance counters). (Incidentally, there may also be case where a reader does not especially care about the temporal precision of a value, i.e., stale data may be good enough for some uses.)

> The complexity would be in the cache coherency protocol and how to send it to the core. The
> difficulty I guess would be in providing it to that register only, as a one-shot deal.

The larger address space of memory would also seem to facilitate scalability. (The MIPS MultiThreading Application Specific Extension defined Inter-Thread Communication Storage, which seemed a bit strange to me. Each 64-bit cell could be addressed by one of sixteen views, using 6 through 3 of the address, which provide different atomic functionality.)
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ARMv8 getting atomic operationsdmcq12/02/14 05:32 PM
  ARMv8 getting atomic operationsMaynard Handley12/02/14 07:33 PM
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      ARMv8 getting atomic operationsLinus Torvalds12/03/14 11:15 AM
        ARMv8 getting atomic operationsanon12/03/14 05:08 PM
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            Guaranteed transactionsanon12/03/14 08:38 PM
              Avoiding ping pongPaul A. Clayton12/04/14 09:11 AM
                Avoiding ping ponganon12/04/14 10:15 AM
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                        Avoiding ping pongLinus Torvalds12/05/14 12:58 PM
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                              Avoiding ping pongJouni Osmala12/08/14 02:45 AM
                                Avoiding ping ponganon12/08/14 05:44 AM
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                                                        Why read RWT or Reddit when you can get journalists to do it for you?Eric Bron01/03/15 02:54 PM
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                                                            Why read RWT or Reddit when you can get journalists to do it for you?Eric Bron01/07/15 07:41 AM
                                                              Manycores vs multicoresjuanrga01/10/15 04:14 PM
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                                                        Intentionally picking a competitors slow part is cheating ...Mark Roulo01/08/15 06:37 PM
                                                          Intentionally picking a competitors slow part is cheating ...coppice01/08/15 11:38 PM
                                                            Intentionally picking a competitors slow part is cheating ...Mark Roulo01/09/15 09:13 AM
                                                              Intentionally picking a competitors slow part is cheating ...Anon01/10/15 02:00 AM
                                                              Intentionally picking a competitors slow part is cheating ...David Hess01/11/15 01:03 PM
                                                            Intentionally picking a competitors slow part is cheating ...someone01/09/15 10:31 AM
                                                              Intentionally picking a competitors slow part is cheating ...coppice01/12/15 09:45 PM
                                                                Intentionally picking a competitors slow part is cheating ...coppice01/12/15 09:47 PM
                                                                  Intentionally picking a competitors slow part is cheating ...Michael S01/13/15 07:53 AM
                                                                    Intentionally picking a competitors slow part is cheating ...coppice01/13/15 09:44 AM
                                                                      Intentionally picking a competitors slow part is cheating ...Michael S01/13/15 10:01 AM
                                                                        Intentionally picking a competitors slow part is cheating ...coppice01/13/15 08:35 PM
                                                                      Core sizesjuanrga01/13/15 12:28 PM
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                                                            Why read RWT or Reddit when you can get journalists to do it for you?Mark Roulo01/09/15 12:59 PM
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                                                            Why read RWT or Reddit when you can get journalists to do it for you?Gabriele Svelto01/11/15 12:53 AM
                                              Why read RWT or Reddit when you can get journalists to do it for you?Fake Linus Torvalds01/03/15 12:14 PM
                                                Why read RWT or Reddit when you can get journalists to do it for you?Rob Thorpe01/03/15 08:25 PM
                                          Avoiding ping pongMaynard Handley12/09/14 11:33 AM
                                            Avoiding ping pongPatrick Chase12/09/14 01:54 PM
                                              Avoiding ping pongMaynard Handley12/09/14 06:56 PM
                                      Avoiding ping pongSalvatore De Dominicis12/09/14 08:51 AM
                                        Avoiding ping pongPatrick Chase12/09/14 02:00 PM
                                      Avoiding ping pongook12/11/14 03:31 AM
                                      Avoiding ping pongArt Scott12/19/14 10:19 PM
                                        Avoiding ping pongEric Bron nli12/20/14 04:05 AM
                                      What about specialization?Troll?01/02/15 07:55 AM
                                        What about specialization?Ungo01/04/15 03:27 PM
                                      Avoiding ping pongfewwef01/05/15 08:16 PM
                                      Avoiding ping pongV.Krishn01/08/15 06:11 AM
                                    Avoiding ping pongGabriele Svelto12/08/14 07:32 PM
                                    Avoiding ping ponganon12/08/14 11:37 PM
                            Avoiding ping pongKonrad Schwarz12/10/14 06:23 AM
                              Avoiding ping pongLinus Torvalds12/10/14 11:56 AM
                          Object reference lockingDavid W12/08/14 11:36 PM
                            Object reference lockingPatrick Chase12/09/14 04:52 PM
                              Object reference lockingDavid W12/11/14 05:18 AM
                    ISA != interface for "most programmers"Paul A. Clayton12/04/14 03:34 PM
                      ISA != interface for "most programmers"rwessel12/04/14 07:50 PM
                  Interesting! (exporting hot lines/cache-aware ISA); "Please sir, I want some more" (NT)Paul A. Clayton12/04/14 02:26 PM
                  Avoiding ping pongMichael S12/06/14 03:48 PM
          ARMv8 getting atomic operationsLinus Torvalds12/04/14 12:05 PM
            LL/SC idiom recognition is not admitting RMW superiorityPaul A. Clayton12/04/14 02:34 PM
            ARMv8 getting atomic operationsanon12/04/14 10:17 PM
    ARMv8 getting atomic operationsPatrick Chase12/03/14 12:09 PM
  limited ordernksingh12/04/14 10:17 PM
    I didn't understand this either. (NT)Konrad Schwarz12/04/14 10:32 PM
    limited orderdmcq12/05/14 02:13 AM
    limited orderbakaneko12/05/14 09:11 AM
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