By: Matt Sayler (firstname.lastname@example.org), June 27, 2007 11:39 am
Room: Moderated Discussions
" - Basically the MMU simply does not operate as specified/implimented
in previous generations of x86 hardware. It is not just buggy, but
Intel has gone further and defined "new ways to handle page tables"
(see page 58).
- Some of these bugs are along the lines of "buffer overflow"; where
a write-protect or non-execute bit for a page table entry is ignored.
Others are floating point instruction non-coherencies, or memory
corruptions -- outside of the range of permitted writing for the
process -- running common instruction sequences."
Ignore for a moment the tone, and concentrate on the substance...
How significant were the TLB handling changes?
In general, do Core2 chips seem to be more or less buggy than previous iterations? Are errata par for the course as we approach billion-transistor commodity MPUs?