Intel’s Long Awaited Return to the Memory Business

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Graphics is a focal point of the upcoming Haswell platform, necessitating a high bandwidth memory solution. To deliver high performance Intel is returning to the DRAM market, which it exited in 1985. The memory that ships with Haswell will be a custom embedded DRAM mounted in the package and manufactured on a variant of Intel’s 22nm process. By avoiding the commodity memory market, Intel will preserve high margins by cannibalizing discrete GPUs and dedicated graphics memory.

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Microservers must Specialize to Survive

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The server market is at a potential inflection point, with a new breed of ARM-based microserver vendors challenging the status quo, particularly for cloud computing. We survey 20 modern processors to understand the options for alternative architectures. To achieve disruptive performance, microserver vendors must deeply specialize in particular workloads. However, there is a trade-off between differentiation and market breadth. As the handful of microserver startups are culled to 1-2 viable vendors, only the companies which deliver compelling advantages to significant markets will survive.

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Computational Efficiency for CPUs and GPUs in 2012

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New compute efficiency data shows GPUs with a clear edge over CPUs, but the gap is narrowing as CPUs adopt wide vectors (e.g. AVX). Surprisingly, a throughput CPU is the most energy efficient processor, offering hope for future architectures. Our data also shows some advantages of AMD’s Bulldozer, and the overhead associated with highly scalable server CPUs.

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IBM z196 Mainframe Architecture

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IBM’s mainframes are the oldest line of computers, dating back to 1964 and occupy a special place as the world’s first instruction set architecture. This longevity and extreme backwards compatibility are responsible for perhaps the most lucrative computer franchise. IBM’s z196 is the first mainframe with an out-of-order CMOS microprocessor, and also the first with an integrated L3 cache. These two innovations are largely responsible for a 30-40% improvement in performance over the previous generation z10.

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ISSCC 2012 Preview

Highlights of the upcoming 2012 ISSCC include the first 22nm disclosures from Intel and several SoC papers from AMD, Cavium Networks and Oracle. Looking out further to the future, the clear focus is power consumption. There are several papers from Intel on low-power logic, one from IBM discussing 3D integration of embedded DRAM and a third from Fujitsu on system level power for the K supercomputer.

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22nm Design Challenges at ISSCC 2011

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As Moore’s Law continues, each new generation of semiconductor manufacturing is ushered in by new challenges, hurdles and solutions. At ISSCC 2011, a panel with speakers from Global Foundries, IBM, Intel, Renesas and TSMC discussed manufacturing and circuit design interactions at the upcoming 22nm node. Industry leaders have reached a broad technical consensus, although with several subtle differences. This report explores the key challenges and solutions at 22nm; focusing on variation and co-optimization between design and manufacturing. As a result of the needed collaboration, understanding of physical design and manufacturing is even more critical to cutting edge chip development and achieving good performance, power and yields.

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IEDM 2010 Process Technology Update

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The integration predicted by Moore’s Law is fundamentally driven by advances in semiconductor manufacturing. One of the key challenges is scaling to ever finer and denser geometries, while improving the performance of transistors. IEDM and the VLSI Symposium are the premier venues to discuss the challenges and opportunities for future process technologies. No commercial 22nm process technologies were presented at IEDM 2010, but in the last two years a number of advances have been disclosed, both for high performance and low power applications. This article describes several 32nm and 28nm nodes from Intel, IBM’s Common Platform and TSMC, plus novel applications such as IBM’s 32nm eDRAM that have been disclosed at IEDM and VLSI.

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Computational Efficiency in Modern Processors

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The computer industry is on the cusp of yet another turn of the Wheel of Reincarnation, with the graphics processor unit (GPU) cast as the heir apparent of the floating point co-processors of days long gone. Modern GPUs are ostensibly higher performance and more power efficient than CPUs for their target workload, and many companies and media outlets claim they are leaving CPUs in the dust. Is this really the case though? This article explores the quantitative basis for these claims, with some surprising results.

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Hot Chips XXI Preview

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Hot Chips 21 is nearly upon us, and with it comes updates from the major processor vendors and players in the PC industry and beyond. Key themes this year include CPUs, chipsets, FPGA and GPU co-processors and academic parallelism research. Our preview will briefly discuss and analyze some of the more interesting topics, with CPU highlights including AMD’s Magny Cours, Fujitsu’s SPARC64-VIIIfx, IBM’s POWER7, Intel’s trifecta of Moorestown, Beckton/Nehalem-EX and Westmere, and Rainbow Falls from Sun. In the broader ecosystem, there will be presentations on OpenCL, Ion from Nvidia, TI’s OMAP SOC for mobile phones, and three major parallelism labs – Berkeley, Illinois and Stanford.

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Process Technology at IEDM 2008

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David Kanter discusses 32nm process technologies presented at IEDM 2008 and VLSI 2009, including a discussion of high-k dielectrics and metal gates, immersion lithography and double patterning. Results from key manufacturers such as Intel, IBM/AMD, TSMC, Toshiba and others are discussed, analyzed and compared against previous generations using metrics for density (logic and SRAM) and switching speed metrics (for NFETs and PFETs).

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