IEDM 2005: Selected Coverage

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The 2005 International Electron Devices Meeting (IEDM) was held in the Hilton Hotel on Connecticut Ave in Washington DC from December 4 through December 7. In the four day period, 1800 attendees from all over the world listened to and examined materials presented on the state of the art in the field of semiconductor devices and manufacturing techniques. Over the 4 day period in snowy Washington DC, IEDM 2005 provided the attendees with: short courses presented by industry experts on lower power CMOS technology platform and next generation semiconductor manufacturing, evening panel discussions on the scalability of flash memory devices and the sustainability of growing semiconductor R&D budget requirements, three keynote speeches, and over 240 technical presentations. IEDM 2005 presented the latest trends in semiconductor process scalability, scalability that has immediate and long term impacts on the design and implementation of all semiconductor devices. Unfortunately, due to the sheer size and scale of IEDM, it is impossible to provide comprehensive coverage of all 240 technical presentations, panel discussions, keynote speeches and short courses. This article focuses on several important trends and selected presentations from IEDM 2005.

Moore’s Law Lives: 2X Smaller, Faster and or Lower Power

In his landmark paper written in 1965, Dr. Gordon Moore made the observation that the number of integrated components per (semiconductor) device has increased by a factor of two per year in the time period between 1959 and 1965. In the same paper, Dr. Moore further asserted that this rate of improvement could continue for another 10 years – until at least 1975. In the 4 decades since he made the observation, Dr. Moore’s observation has seen minor revisions, and it is now honored as a “law”. This codification reflects the fact that the number of transistors on semiconductor devices has continuously increased at the observed exponential rate through the last 4 decades. Strictly speaking, Moore’s Law only describes the rate of increase in transistor density.

However, in the last 4 decades, transistors were also typically faster and consumed less power in each successive process generation. As a result, the repetition of Moore’s law with each process generation also trained the public at large to expect comparable rates of transistor performance improvements in each process generation. Unfortunately, one theme that emerged from the numerous technical presentations, seminars and panel discussions at IEDM 2005 is that the era of trade-off free linear scaling has ended, and the era of trade-off based process scaling continues. In essence, future process generations will no longer automatically bring transistors that follow the historical scaling trends in density, performance and power when compared to transistors in previous process generations.

Instead, future process technologies (even more so than prior process technologies) will have to be carefully tuned to target density, performance or low power. Individually, a specially targeted process could continue to increase density by 2X, improve intrinsic transistor performance increase by approximately 37%, or reduce transistor state switching energy by (0.7)3 in each process generation [6,9]. However, no single process would be able to continue on all of these historical scaling trends simultaneously. For example, on IBM’s low power and low cost 65 nm process technology, density scaling is continuing on the logarithmic trend of halving SRAM cell sizes from the 90 nm process node, but the SRAM cell size scaled at a slower rate in IBM’s performance optimized process technology in shrinking from the 90 nm node to the 65 nm node. This change means that VLSI design engineers and chip architects must now work even closer together with semiconductor device and process engineers to carefully tune separate lines of process technologies for transistor density, performance or lower power consumption characteristics based on the target application.

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