Process Technology at IEDM 2008

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The Industry Moves to High-K/Metal Gates

As David Wang pointed out in our prior coverage of IEDM 2007, one of the challenges for semiconductor companies is that many of the familiar parameters which determine performance, density and power can no longer be scaled down or manipulated by engineers.

At the 45nm node, physical gate oxide thickness (also referred to as Tinv or Tox) could no longer be decreased while maintaining control over leakage. As the silicon oxy-nitride (SiON) gate material becomes thinner, tunneling becomes more and more problematic and manifests as substantially increasing gate leakage. Consequently, most manufacturers chose to keep Tox >1.2nm at the 45nm node to keep leakage under control. The consensus was clear – the industry would have to move from SiON to high-k dielectrics and metal gates, to keep the Effective Oxide Thickness (EOT) constant, while shrinking the physical thickness of the oxide for 32nm and beyond.

Bucking the trend, Intel demonstrated record drive currents with their 45nm process using high-k dielectrics and metal gates. Intel had been shipping products (Penryn) manufactured in 45nm since late 2007, and their IEDM paper in 2007 was the industry’s first look at the results achievable with a production worthy high-k/metal gate approach.

At IEDM 2008, the focus of the process technology session was the industry-wide transition to 32nm. There were five different papers on 32nm processes and every one relied on high-k dielectrics and metal gates to increase control over the channel and decrease leakage.

The transition to high-k/metal gates was quite challenging for the industry and accelerated the consolidation of digital logic manufacturers. The 45nm process was a turning point for several former stalwarts that ultimately chose to cease internal development of new process technologies.

Both Texas Instruments and Fujitsu were known for their high performance process technology and partnered with various high performance CPU design teams, but both opted to collaborate with TSMC for future development and manufacturing. Whether these decisions were solely due to the development costs of bringing a high-k/metal gate process into production is far from clear, but that additional complexity couldn’t have made the situation easier for either company. Both companies were beset by financial pressures, and process development is an incredibly expensive endeavor that constantly escalates in cost [1].

The high cost of R&D, and perhaps also the scarcity of talent, has accelerated development collaboration between competitors – termed ‘cooptition’, where R&D costs are shared between otherwise competing firms. IBM, with it’s world-class research staff has been the main driver and beneficiary of this trend, collaborating on both SOI and bulk development with a coterie of partners that, unlike IBM, have volume production to fund development. Historically, IBM’s partners were smaller logic IDMs and foundries (such as AMD and Chartered), but they recently started to work with STMicroelectronics, Toshiba and NEC, some of the largest IDMs. The leading logic manufacturing firms, Intel and TSMC, have eschewed any corporate development alliances (although they collaborate on basic research through SEMATECH, IMEC and others); their revenues and scale can easily justify the investments needed to continue down the path of Moore’s Law.

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