Historic Process Technologies Comparison
Table 1 below is an enhanced version of our Process Technologies Cross Comparison chart, started by David Wang in his 2005 IEDM coverage. This new version has a bit more information, including exposure technique, gate materials, and contacted gate pitch. We have also added some papers from past conferences and this year’s crop of papers from IEDM, plus the IBM paper from VLSI. Unfortunately, the image below is a thumbnail of the actual chart, to view a more legible full resolution version, simply click on the chart (and make sure the window is wide enough to accommodate a 1207 pixel wide image).
Update: Two eagle-eyed readers (Jokerman and Hans de Vries) discovered updated information on Intel’s 32nm process and TSMC’s 28nm process. Intel’s PFET Ion was described as 1210uA/um in their IEDM paper, but reported as 1310mA/um in the presentation – indicating improvements made in the months between the paper submission and the actual conference. According on an online comment, TSMC’s 28nm process has NFET/PFET drive currents of 1360/960uA/um at Ioff of 100nA/um.
The exposure field indicates whether single exposure (SE) or double patterning (DP) was used. There are a variety of DP techniques, but litho-etch-litho-etch (LELE) is the predominant approach for cutting edge logic technologies and uses two different resists and exposures. The process technologies described above are almost certainly all using LELE.
Litho-freeze-litho-etch (LFLE) technique improves over LELE by using only a single etching, improving throughput with fewer steps and yield by reducing overlay issues; but is not quite ready for production at the moment.
Self aligned spacers are an elegant option for printing highly regular structures, with fewer yield and overlay issues. It is more expensive and doesn’t work for the random layouts used in logic oriented processes; although work is being done on decomposing logic processes into several orthogonal mask layers, where each individual layer is regular.
Double exposure, which only uses a single resist (but exposes twice) is an ideal technique. It only adds a single step (the additional exposure) and has vastly fewer overlay and yield issues compared to the alternatives, since the wafer does not leave the stepper. However, to improve lithographic resolution with double exposure, a non-linear resist that can ignore light levels below a certain threshold is needed. SEMATECH and others are currently researching viable resist candidates, and double exposure is not used in production.
The gate materials field indicates the gate stack. Many of the older papers that are blank in our chart used SiO2 and polysilicon, some more modern processes (typically 90-45nm) use SiON and polysilicon. Of course, the most advanced processes are using high-k/metal gates. One exception this year is paper 27.5, a 40nm low power and density optimized process from Toshiba and NEC that uses a hafnium doped silicate for the dielectric, but with a standard polysilicon gate.
The contacted gate pitch dictates the spacing for logic transistors, and hence is a key metric for logic density. In that regard, it is the dual to the SRAM bit cell area, which is a density metric for storage elements in modern chips.
When thinking about the data that is reported at IEDM and VLSI, it is important to take the information with a grain of salt. The papers at these conferences sometimes contain a bit of marketing and can be slightly misleading (or sometimes outright deceiving if read simplistically). For instance, consider SRAM density – a number that is touted by most manufacturers.
The density of an individual SRAM bit cell is interesting, but the density of the array (which includes bit cells and I/Os) is more relevant for designers. All things being equal, smaller bit cells store less charge and tend to require larger I/Os to read out the data. Some manufacturers report the size of a bit cell in a large array (say 100Mbit), while others tend to use cells for a small array (say 10Mbit) or simply report stand-alone SRAM cell size. Additionally, there is rarely any mention of the reliability (in terms of soft-error rates) or manufacturability (in terms of yield) of bit cells – the smaller a cell, the more susceptible it becomes to soft errors and defects, which in turn would require ECC or other measures. Last, manufacturers rarely report access times for their SRAM arrays – which as mentioned previously is a key trade-off.
To highlight this, the author reviewed 9 papers from ISSCC, examining the SRAM bit cells used in last level caches (i.e. the densest SRAM), compared to the claimed bit cell size in IEDM process papers. In a given process technology, the SRAM cells actually used in production MPUs were about 5-15% larger than those reported in IEDM papers. For a latency sensitive L1 cache, the SRAM cells might be 50-70% larger than the reported SRAM cell in an IEDM paper, as the cache designers will trade density for performance.
All these factors play into the reported SRAM cell size. There are plenty of other factors impacting drive current, contacted gate pitch and other key process parameters. These differences should serve as a reminder that a single number cannot adequately capture the complexities of the trade-offs and optimizations facing chip and process engineers.