In most years, IEDM is host to a number of technical papers on semiconductor manufacturing from both industry and academic research. The scope of IEDM is very broad and encompasses all kinds of semiconductors and related technologies, from the relatively common logic, DRAM and display manufacturing, to exotic materials and long ranging research like graphene or nano-wires. These papers and presentations describe the state-of-the-art for manufacturing technologies and also upcoming challenges and potential solutions. Conveniently the whole semiconductor industry is on a roughly 24-month cadence that coincides with IEDM in San Francisco (with alternating years in Washington DC). So ordinarily, the leading manufacturers and foundries will disclose the details of their latest process technology to a crowd of customers, partners, competitors and interested researchers.
Historically, the presentations on digital logic manufacturing were drawn from the ranks of leading IDMs and foundries including Fujitsu, IBM, Intel, TSMC, UMC, Texas Instruments and Toshiba. However, the number of IDMs has thinned beyond 45nm, both due to the cost of manufacturing and the complexity of novel techniques such as high-k gate dielectrics and metal electrodes (sometimes called simply high-k/metal gates or HKMG). Fujitsu and TI are working with TSMC for 32nm and beyond and even Toshiba has indicated they will begin to work with a foundry. UMC has also changed their strategy and will slow their move to new nodes. That leaves three leading edge camps for digital logic – Intel, TSMC and the IBM alliance including Global Foundries and Samsung. At IEDM 2008 these three groups described their respective approaches for the 32nm node, including high-k/metal gates and the resulting performance and density metrics.
In a rather surprising turn of events, none of the leading manufacturers described a production ready 22nm process technology at IEDM 2010. There was one presentation on a research effort from TSMC, but certainly nothing that could be construed as ready for commercialization. Skeptics might interpret this unexpected silence to mean that the continued scaling of CMOS to new nodes (and thus Moore’s Law) is in danger, due to power or performance considerations. However, that is unlikely to be the case. Silicon scaling has encountered significant challenges starting at the 65nm node, but they have consistently been managed. Improving transistor density has been accomplished through techniques such as double exposure and immersion lithography, which improve the resolution of critical features. Transistor performance (namely the drive strength) has been more difficult, as many existing techniques have collided with the laws of physics and ceased to scale to smaller dimensions. However new approaches, such as high-k/metal gates and strained silicon continue to scale performance and power efficiency at new nodes. More to the point, there were plenty of presentations from industry and academia discussing the challenges and potential solutions for scaling at the 15nm node and beyond, suggesting that the outlook for CMOS is good for at least the next decade.
So the absence of papers is unlikely to signify difficulty for the industry as a whole, but rather that leading edge manufacturers wish to withhold certain details of their 22nm process technology for the time being. There is certainly a good precedent for this tactic; Intel’s 45nm process (the first with HKMG) was not disclosed until IEDM 2007, both so they could do their own public announcement and also avoid disclosing certain details such as performance and density metrics. So the most plausible interpretation of the absence of 22nm presentations is that manufacturers are using rather innovative approaches and they are leery of tipping their hands too early – especially Intel, which is roughly 12 months ahead of everyone else to begin with.
For example, IBM and their partners announced some changes concerning the 22nm process node. As was already widely expected, they indicated that they will discontinue work with a gate first HKMG transistor stack and instead go with a gate last approach – as pioneered by Intel and adopted by TSMC. This move had been presaged by rumors of discontent amongst IBM’s partners and the continuing yield related delays with Global Foundries’ 32nm gate first process. The argument put forth by IBM is that at 32nm, the density advantages of gate first were about equal with the yield losses, while 22nm and below tipped the scale in favor of gate last. This is probably true – but only for IBM’s very specific applications; it’s clear that TSMC and Intel (both of which are vastly higher volume) believed otherwise, and it seems likely that gate last was the best choice for more general applications. Announcing such a change at IEDM or VLSI would require a paper describing the expected improvements from a move to gate last – which is simply more information than IBM or their partners wish to share at the moment.
This article will discuss the major process technology announcements over the last two years, particularly those at IEDM and the VLSI Symposium from 2009 and 2010. The major announcements focus on SOC optimized process technologies at the 32nm or 28nm node, rather than any new high performance nodes. The additional details on high performance process technologies are largely incremental, or about specific applications (e.g. IBM’s eDRAM).