The integration predicted by Moore’s Law is fundamentally driven by advances in semiconductor manufacturing. One of the key challenges is scaling to ever finer and denser geometries, while improving the performance of transistors. IEDM and the VLSI Symposium are the premier venues to discuss the challenges and opportunities for future process technologies. No commercial 22nm process technologies were presented at IEDM 2010, but in the last two years a number of advances have been disclosed, both for high performance and low power applications. This article describes several 32nm and 28nm nodes from Intel, IBM’s Common Platform and TSMC, plus novel applications such as IBM’s 32nm eDRAM that have been disclosed at IEDM and VLSI.
David Kanter discusses 32nm process technologies presented at IEDM 2008 and VLSI 2009, including a discussion of high-k dielectrics and metal gates, immersion lithography and double patterning. Results from key manufacturers such as Intel, IBM/AMD, TSMC, Toshiba and others are discussed, analyzed and compared against previous generations using metrics for density (logic and SRAM) and switching speed metrics (for NFETs and PFETs).
David Wang provides an overview of disclosures at IEDM 2007, including presentations from TSMC, Fujitsu, IBM, Toshiba, Sony, AMD, NEC on their 45nm immersion lithography processes and Intel’s 45nm high-K and metal gate process which relies on dry lithography.
Introduction The 2005 International Electron Devices Meeting (IEDM) was held in the Hilton Hotel on Connecticut Ave in Washington DC from December 4 through December 7. In the four day period, 1800 attendees from all over the world listened to and examined materials presented on the state of the art in the field of semiconductor […]
Partial coverage of IEDM 2003 Day 2, focusing on AMD and Intel process technologies