What’s Next for Moore’s Law? For Intel, III+V = 10nm QWFETs

On the eve of the 50th anniversary of Moore’s Law, the future of silicon CMOS is an open question. Scaling to future process technologies is increasingly challenging; Intel ran into yield problems at 14nm, and many other companies are grumbling about the increase in wafer costs. At the same time, the performance and power benefits from shrinking to a new process have changed.

Historically, transistor performance (i.e. delay), operating voltage, and transistor current all scaled in tandem with geometry. As a result, the power consumption of a transistor scaled down quadratically, and overall power density stayed constant – even as the transistor density exploded (courtesy of Moore’s Law). This phenomenon was codified by Robert Dennard and a team of researchers from IBM in 1975, hence the name – Dennard scaling.

However, Dennard scaling broke down in the early 2000’s as David Wang noted in his report on IEDM 2005. Performance could no longer be increased through geometry alone, and power became a tremendous problem. Power consumption comes in two flavors – static power, due to leakage current through the transistors, and dynamic power, due to switching activity in transistors.

As transistors became ever smaller, leakage grew from a minor nuisance that could be ignored by digital circuit designers, into a serious problem. Leakage also increases dramatically as the threshold voltage (i.e., the point when the transistor turns ‘on’, which is typically controlled by doping the transistor) decreases. Dynamic power is proportional to the square of voltage – even a small reduction in supply voltage dramatically improves power efficiency. Unfortunately, classic CMOS behaves poorly at supply voltages below 1V, due to the bandgap of silicon, and errors become much more common. Moreover, the threshold voltage is typically reduced in conjunction with the operating voltage to ensure good performance; however reducing the threshold voltage is difficult because of the associated leakage problems.

Architectural and circuit design techniques can reduce leakage and dynamic power. For example, power gating eliminates leakage currents, but requires additional area for the power gates. As another example, Intel began using 8-transistor (8T) register file cells for their L1 caches at 45nm. The larger 8T cells are more resilient against soft errors and enable lower voltage operation at the cost of extra area. Overall though, these techniques are not nearly as powerful as changes in process technology.

The biggest steps forward have come from the introduction of new materials and new transistor architectures into silicon CMOS. At the 90nm node Intel adopted strained silicon, which increased the mobility of charge carriers in the transistor channel, thereby improving the drive current and performance of transistors. Shortly thereafter, leakage went from a noticeable physical effect to a looming catastrophe. Fortunately, a solution was at hand. High-k gate dielectrics (HfO2) and metal gate electrodes dramatically reduce leakage and improve transistor drive strength. These novel materials were first integrated into production silicon CMOS at Intel’s 45nm process, with wider industry adoption at 28nm.

The industry next turned to FinFETs, which alter the basic geometry of the transistor. Instead of forming the gate above the transistor channel, a FinFET wraps the gate around the transistor channel on three sides. The net result is substantially better control over threshold voltage, which enables operating voltages to decrease from around 1V down to 0.8V while maintaining transistor performance and keeping leakage under control. Intel’s 22nm node was the first to adopt FinFETs and went into production in late 2011. The rest of the industry waited for several years to use FinFETs – Samsung is currently in production for the Exynos 7420 in the Galaxy S6, and TSMC will be in production later in 2015.

Strained silicon, high-k/metal gates, and FinFETs have sustained Moore’s Law and CMOS performance, but each introduces new steps (e.g., atomic layer deposition for HKMG) that add to wafer cost. Moreover, process steps that draw features smaller than 80nm require double patterning techniques; each extra exposure decreases wafer throughput and increases costs. For most foundries, the 20nm node had minimal performance benefits compared to 28nm, and many fabless customers skipped 20nm and instead waited for FinFETs. As a result of the rising costs and uncertain benefits, some semiconductor companies have questioned the wisdom of pursuing Moore’s Law.

This sets the stage for the next challenge – finding a transistor that provides high performance with supply voltages below 0.7V, and will enable Moore’s Law to continue to 10nm and beyond.

My prediction: High-mobility QWFETs for Intel at 10nm

At this point, I’d like to share a series of predictions concerning Intel’s 10nm node. I first made these predictions in private with a few friends and colleagues back in 2012, but now is the time to make them rather public.

  1. The industry will adopt Quantum Well FETs (QWFETs) that use a fin geometry and high-mobility channel materials to achieve excellent transistor performance at nominal operating voltages around 0.5V (compared to roughly 0.7V for FinFETs)
  2. The industry will adopt III-V compound semiconductors (most likely In0.53Ga0.47As, alternatively InSb) for the n-type QWFET channel
  3. The industry will adopt strained Germanium (most likely) or III-V materials (as an alternative) for the p-type QWFET channel
  4. Intel will adopt QWFETs at the 10nm node (most likely), which will probably go into production in late 2015 or early 2016 (alternatively at 7nm in 2017 or 2018)
  5. Intel will probably co-integrate conventional transistors and QWFETs, it is less likely (but possible) that the company will use separate substrates that are packaged together to optimize cost
  6. The rest of the industry (e.g., Samsung, TSMC, Global Foundries) will wait until the 7nm node to use QWFETs

Figure 1 shows the conceptual layout of an experimental InGaAs planar Quantum Well FET, taken from an Intel research paper. The quantum well is formed when the charge carriers (e.g., electrons for NFETs) in the InGaAs are confined and act as if the InGaAs is essentially 2-dimensional. In a planar n-type QWFET, this is achieved with an extremely thin (10nm) channel material, where the bottom barrier constrains the electrons on one side, and the gate constrains the electrons from the top. A planar p-type QWFET can be created using strained Germanium and constraining holes in the channel (rather than electrons).

InGaAs planar QWFET

Figure 1. Experimental InGaAs planar QWFET. Source: Intel, IEDM 2009

Figure 2 shows the conceptual layout of an experimental InGaAs Quantum Well FinFET, taken from a subsequent Intel research paper. The mechanics of a QW-FinFET are slightly different, since FinFETs control the transistor from three sides. Essentially, the FinFET geometry confines the electrons from three sides, with the bottom barrier handling the fourth side – creating a quantum well between them. This enables an approximately cubic shape for the InGaAs channel, compared to the long and narrow channel used in the planar QWFET.

InGaAs Quantum Well FinFET

Figure 2. Experimental InGaAs Quantum Well FinFET. Source: Intel, IEDM 2011

Intel’s Components Research Lab has been working on QWFETs for a little under a decade. The initial work was highly experimental and there was no real indication that III-V and Ge QWFETs would mature into a realistic technology choice. Over time, Intel’s researchers showed that they could tackle a number of major technical problems as outlined by Mike Mayberry of Intel. Once Intel’s researchers showed that it was possible to create FinFET QWFETs, it became clear to me that this technology was headed out of research, into development, and ultimately into processors that would be on the market. I believe that 10nm is the most likely intercept point (it’s possible, but less likely, Intel will wait until 7nm), given the timing of the research and Intel’s historical cadence of new manufacturing technologies.

I made these predictions public for a few reasons. First, I believe that industry experts should make insightful, specific, verifiable predictions that have a definite time horizon. Simply saying that a new process technology will be better is vacuous (if it wasn’t better, who would pay to develop it?). Moreover, any prediction that is not potentially wrong is uninformative (saying someone will win the World Cup is pointless, but predicting Germany in 2014 was impressive!). Similarly, predictions that are not anchored to timelines are less valuable. Second, I want to create a record of my predictions so that it is clear what was correct and what was mistaken. This is particularly valuable, since I can explain in the future why some of my projections were correct, and why some were not. Simply saying that ‘things changed’ is not a good explanation, instead, it is very useful to explain why a particular theory seemed correct and reconcile that with reality.

In reality, it will take months or years for Intel and the rest of the industry to reveal their plans for 10nm and 7nm. In the mean time, this informed speculation should lead to some interesting discussions. For anyone interested in more detailed projections (e.g., performance, area, fabrication techniques, etc.), please contact me directly.

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