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One of the most remarkable aspects of IEDM 2010 was the absence of papers describing production 22nm and 20nm manufacturing. As it turns out, Intel decided to delay publication to separately announce their novel 3-dimensional FinFET transistor architecture for 22nm. Intel’s 22nm node will use bulk silicon, with a fully depleted tri-gate transistor structure. Instead of having the channel sandwiched between the gate (top) and the silicon (bottom), the tri-gate transistor wraps the gate around three sides, with the silicon underneath. Early research often focused on a double gate FinFET, where the gate is on the sides of the channel, but not the top. To avoid confusion (and do a bit of marketing), Intel refers to their design as a tri-gate transistor, although it is a type of FinFET.
In a conventional planar transistor, the current flowing through the channel is closely related to the width (W) of the device, divided by the length (Leffective). As the industry scales to smaller nodes, it is ideal to decrease Leffective, which improves the drive strength of the transistor. However, shorter transistors have less control over the channel and exponentially higher sub-threshold leakage. To control leakage, the channel is heavily doped, which makes everything more susceptible to variability (particularly random dopant fluctuations). Variability is one of the biggest 22nm challenges for the industry.
Figure 1 – Planar and Tri-Gate FinFETs, courtsey of Intel
In a tri-gate transistor, the gate surrounds the channel on all three sides and has much better control so that all the charge below the transistor is removed (i.e. fully depleted). The stronger control decreases sub-threshold leakage, so the transistor is much better at shutting off. This reduces (or eliminates) dopant variability as well, because less (or no) doping is needed to control the channel. However, variation in the height and width of the tri-gate is now an issue, and needs to be tightly controlled. Additionally, the width (Weffective) of a tri-gate transistor is the sum of all three sides – twice the fin height plus the fin width. A TSMC paper from IEDM 2010 concluded that a tri-gate FinFET can have nearly 2X the effective width of a planar transistor, in the same area. To build transistors with different performance and leakage, multiple fins are ganged together and share a single gate – essentially multiplying the width; the gate length can also be adjusted. For future scaling, the height of the fin can be increased to maintain performance.
Intel reported a substantially steeper sub-threshold slope (the slope from 0V to 0.4V in Figure 2) for the tri-gate transistors. The sub-threshold slope measures how fast the device can switch from off to on – a key element of performance. This is a significant benefit that Intel can harness to improve frequency, active power, idle power or a combination of the three. The 22nm tri-gate transistors are 18% and 37% faster at 1V and 0.7V than Intel’s 32nm transistors (Figure 2). The saturated drive currents (typically reported at IEDM) for these tri-gate transistors could exceed 2mA/um – an industry first. The data also suggests that the linear drive strength of Intel’s 22nm process (i.e. when transistors are not fully switched on) will see a very big improvement – closer to the 37% mark. In practice though, Intel’s 22nm chips will not be 37% faster – the actual frequency is determined by the slowest circuits, but significant gains are feasible.
Figure 2 – FinFET Sub-threshold Slope and Gate Delay Improvements, courtsey of Intel
While higher frequency is great for improving CPU performance, it is not always the best choice. For example, GPUs tend to rely on a huge number of more efficient transistors and run about 2-4X slower than a CPU. For scenarios where active power is most critical, the 22nm process can keep the same frequency but lower the operating voltage (e.g. from 1V to 0.8V). Active power falls even faster since P ~ F * V2 and Intel claims 50% less power, so the voltage reduction may be slightly larger in some circumstance. Similarly, transistors could use this headroom to significantly lower leakage power for always-on circuits, instead of changing frequency or active power. While Intel did not cite any specific numbers, it seems likely that an improvement of 1-2 orders of magnitude is realistic given the exponential relationship between leakage and drive currents.
The tri-gate transistors are a tremendous breakthrough in performance and the 22nm process also improves density by the traditional 2X. But it is important to realize that the performance gains Intel is citing are not simultaneous. Transistors will not get 37% faster, 50% more efficient and reduce leakage by 10X all at the same time; nor will entire chips see the same gains as the individual transistor level. Intel’s circuit designers will have to pick and choose how to use the newfound advantages throughout each chip to achieve the best overall results, given the product.
Dr. Mark Bohr and Bill Holt are responsible for development and manufacturing at Intel, respectively. Along with the research group, their teams spent many years examining the technology options and now ramping tri-gate into high volume production. As part of their presentation, they explained the technology options and rationale behind their decision.
The three transistor options that Intel evaluated at 22nm were conventional planar, tri-gate and fully depleted silicon-on-insulator (FD-SOI, sometimes referred to as extremely thin SOI). Scaling bulk transistors to 22nm was the low-risk fallback plan. It is known to work, but with much smaller performance gains and complications from variation. FD-SOI has very similar benefits to a tri-gate device, but is planar. It relies on placing a ~10nm oxide layer between the wafer and a thin layer of silicon, which achieves slightly better isolation than tri-gate and similar benefits. One advantage is that FD-SOI is compatible with body-biasing techniques, which can improve performance. Despite this, there are significant challenges; as with all SOI, it is very hard to build diodes (for static electricity protection) – the oxide layer must be removed. More importantly, it is very expensive. Intel estimates that FD-SOI increases the cost of a finished wafer by 10%, compared to 2-3% for tri-gate. The cost for FDSOI is prohibitive for Intel (and TSMC), precluding it as an option. So the decision came down to whether Intel’s manufacturing group was confident that they could get tri-gates into high volume at 22nm.
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