Intel’s 45nm Surprise: High-k Dielectrics and Metal Gates

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Manufacturing Versus Design

With the announcement of the Core microarchitecture at Spring IDF of last year, Intel publicly stated their intentions to regain the lead in the world of x86 microprocessors. In a rather impressive fashion, the folks at Intel got down to business and executed almost flawlessly on their plans in 2006. Pretty much every product in the MPU portfolio was replaced by a newer, faster and better version. The first processors using the new microarchitecture were delivered early in March, and easily set new records for performance. In October, Intel followed up by releasing the first quad core processor: Clovertown. AMD abruptly found the tables turned on them, facing a performance deficit in many workloads. The results were somewhat predictable; in the last quarter, AMD experienced market share losses and a negative impact on their bottom line. This was to some extent masked by the costs of the ATI acquisition, but not entirely. These conditions are largely expected to remain the same, given Intel’s need to regain market share, until the middle of the year, when AMD will release ‘Barcelona’ a new microprocessor.

However, what happens beyond the middle of the year is subject to quite a bit of uncertainty, with rhetoric issuing from both camps. AMD has claimed an advantage based on performance models, which are extremely accurate but may not account for faster speed grades from Intel, of around 10-15% for TPC-C and 40% for SPECfp_rate. The latter is likely to be somewhat of an outlier, but it is clear that AMD will be strongest in high performance computing workloads. AMD’s performance is largely attributed to microarchitectural improvements and a high level of system integration. Much like the K8, AMD has opted to heavily market their emphasis on processor and system design; focusing on an integrated memory controller, monolithic integration and Hypertransport as their key advantages.

While Intel is the biggest designer of microprocessors, the company bills itself as the largest semiconductor manufacturer and approaches problems from that perspective. Intel’s current development strategy is a perfect example. The ‘tick tock’ model was first coined by Paul Otellini, and is a rhythm for development of products and process technologies at Intel. The first product released on a new process will be a shrink of an existing core, followed by a new microarchitecture a year later.

The benefits of this approach are rather clear. A new process will first be used for a fully characterized and debugged processor design, so most problems that occur will be due to the process. Once any issues that crop up are isolated, future teams will be easily alerted and able to steer clear of them. By the time that a new microarchitecture is released a year later, the process it is using will be fully understood and in high volume production. Consequently, the difficult issues will be strictly microarchitectural. The whole point of this is to reduce risk, and ensure that improvements to Intel’s product line are delivered in a smooth, timely and consistent fashion.

In contrast to AMD’s focus on design, Intel is clearly playing to their long standing expertise in material sciences and manufacturing. On Thursday, Intel held a briefing to demonstrate their advances at 45nm. While most people have read that Intel recently booted four operating systems on the first silicon from the 45nm shrink of the Core microarchitecture (codenamed Penryn), what is more interesting is the underlying silicon that Penryn was fabricated on. Intel’s presentation described advances in their 45nm process; the first commercial manufacturing process to use high-k gate dielectrics and metal gate electrodes. The combination of the two will give Intel a significant advantage for the lifespan of their 45nm process, by substantially reducing leakage and improving performance. This article focuses on the background, technical details and importance of Intel’s 45nm developments.

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