Notes from ISSCC 2001

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This is a collection of comments on interesting new ideas and disclosures related to microprocessors, memory, and related technology presented at the 2001 IEEE International Solid-State Circuits Conference (ISSCC) held earlier this month in San Francisco. Up to five sessions were run concurrently so this personal account is far from exhaustive.

Headhunter’s Dream

Early every February thousands of engineers, managers, professors, and students descend upon the Marriott Hotel in downtown San Francisco for the annual ISSCC Conference. Sponsored by the IEEE Solid-State Circuits Society, the local IEEE section, and the University of Pennsylvania, this global chip ‘Woodstock’ attracts heavy international participation, particularly from Europe and Japan. This year the meeting areas and ballrooms were crowded elbow to elbow, wall to wall with over 3500 attendees, ranging from wide-eyed graduate students to veterans who are continuing to advance chip design after 20 years or more in the industry.

Not for the RISC Averse

Among some industry observers it is commonly accepted wisdom that the processor wars are over and RISC lost. If this were true you would never know it from attending ISSCC 2001. The majority of the microprocessor papers presented described RISC designs. There were two papers presented on the Alpha EV7, one on the Alpha EV68, two PA-8700 papers, one POWER4 paper, one ARM paper, and one MIPS paper. On the CISC side there were two papers on the Pentium 4 and one on a S/390 (IBM mainframe) device. AMD enthusiasts will be disappointed to hear that their favorite MPU house continued its ostensible policy of withholding substantive technical disclosures about current and future products and didn’t present any papers.

Proponents of VLIW for general-purpose applications had to be satisfied with a lone Sun paper on the MAJC 5200 dual processor device. Ironically, it was overshadowed by another VLIW paper that wasn’t even presented. Intel withdrew its paper on McKinley, its second-generation IA-64 processor, for undisclosed reasons. This no-show was widely reported in the trade press, and rekindled rumors about ongoing problems in the joint Intel and HP processor development effort based in HP’s Fort Collins facility. Indeed, Intel veteran Pat Gelsinger’s plenary session invited paper ‘Microprocessors for the New Millenium – Challenges, Opportunities and New Frontiers’, emphasized that semiconductor technological trends will require increased emphasis on greater computational power efficiency and insensitivity to memory latency. These trends favor TLP oriented techniques such as chip level multiprocessing and multithreading, paths Gelsinger himself suggested in his talk, rather than heavily ILP oriented design philosophies such as EPIC.

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