ISSCC 2008 Preview: Silverthorne, Rock, Tukwila and More

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ISSCC 2008 Preview

The International Solid State Circuit Conference is the premier venue for companies to disclose the circuit level innovations that continue to drive the semiconductor industry forward. Papers will be presented on topics ranging from optical transceivers to PLLs and microprocessors. The advance program for ISSCC 2008 was just released online and includes nearly a dozen presentations that are of interest. This short article will preview some of the more interesting papers that will be presented at ISSCC 2008.


The DRAM session at ISSCC includes three notable papers from Intel (14.3), Samsung (14.5) and Hynix (14.6). The first is from Intel and describes a 2Mb macro composed of 2T gain-cell memories that operates at 2GHz in a 65nm logic process with a 2X density advantage relative to SRAM. This paper appears to be from Intel’s research group, and is more of a proof of concept rather than a product oriented technology.

Samsung’s paper focuses on GDDR5 with 6gbps signaling in a 60nm DRAM process. Hynix describes a 3gpbs DRAM interface for GDDR3 that is implemented in a 66nm DRAM process.

The SRAM session includes two papers from Intel (21.1) and IBM (21.2), both focusing on 45nm SRAMs. Intel’s paper focuses on a 153Mbit sub-array with 0.346um2 cells that is used in Intel’s 45nm x86 MPUs. The IBM paper describes a 512Kb macro with 450ps access time implemented in a 45nm SOI process.

ISSCC traditionally includes several papers from the previous IEDM, which is being held next week in Washington DC. Last year, one of the highlighted papers was a discussion of phase-change bridge memory from researchers at IBM Almaden in San Jose.

This year, there are four highlighted papers. The first discusses a low cost self-alignment process for SOI, the second descrbes a 32nm low power process at TSMC and the third details RF performance for IBM’s 45nm process. The last and most important paper from IEDM 2007 is Intel’s presentation of their 45nm high performance logic process (SE6.4), which includes high-K metal gate transistors.

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