ISSCC 2008 Preview: Silverthorne, Rock, Tukwila and More

Pages: 1 2

A RISC Revival?

The Microprocessor track is a perennial favorite, both because the papers tend to be extremely approachable (compared to most other tracks) and highly visible to the public. This year, RISC architectures appear to be experiencing a bit of a renaissance with no fewer than three papers, and three papers dedicated to Itanium or other VLIW architectures.

The first two papers are from Sun Microsystems and discuss the Rock (4.1) and Niagara 3 (4.2) processors, both of which are targeted at 2.3GHz in a 65nm process. Both processors feature 16 cores and Niagara 3 has 32 threads. Rock features 32 threads plus 32 scout threads, out-of-order retirement and transactional memory with high single threaded performance – unlike Sun’s other MPU designs.

A third paper from IBM (4.3) describes a 45nm version of the CELL processor with significant area and power reductions (34% and 40% respectively).

Intel will present two papers on Tukwila, the 65nm Itanium microprocessor. The first (4.6) is a general overview that describes the design as a 699mm2 die with four dual threaded cores, 30MB of cache a memory controller with 34GB/s of bandwidth and 96GB/s of processor interconnect bandwidth. The second presentation (4.7) focuses on circuit design techniques to enable voltage scaling and maintain soft error rates.

The third VLIW oriented presentation is from Tilera (4.4), describing their SoC architecture, which consists of a network of VLIW processors, memory controllers, cache and switches.

The sole CISC paper for ISSCC is actually in the Mobile Processing track (13.1). This paper from Intel describes Silverthorne, an ultra-low power mobile processor. According to the program, Silverthorne is:

A 47M transistor, 25mm2, sub-2W IA processor designed for mobile internet devices…It features a 2-issue, in-order pipeline with 32KB iL1 and 24KB dL1 caches, integer and floating point execution units, x86 front end, a 512KB L2 cache and a 533MT/s front-side bus. The design is manufactured in 9M 45nm High-k metal-gate CMOS and housed in a 441-ball µFCBGA package.

Overall, ISSCC 2008 should have some extremely interesting disclosures. The key highlights include Sun’s Rock processor, which uses scout threads to prefetch data and increase single threaded performance and transaction memory. The Tukwila paper will be the first official disclosure from Intel regarding Quickpath/CSI and the future of Itanium. However, the most relevant presentation is likely to be Intel’s ultra-low power mobile processor, as unlike Tukwila and Rock, it is intended to be a high volume product.

Pages: « Prev  1 2  

Discuss (25 comments)
Tea Sets Amber Jewelry